Commit af180b81 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge branch 'fixes' of git://git.kernel.org/pub/scm/virt/kvm/kvm 

Pull kvm bugfixes from Gleb Natapov:
 "There is one more fix for MIPS KVM ABI here, MIPS and PPC build
  breakage fixes and a couple of PPC bug fixes"

* 'fixes' of git://git.kernel.org/pub/scm/virt/kvm/kvm:
  kvm/ppc/booke64: Fix lazy ee handling in kvmppc_handle_exit()
  kvm/ppc/booke: Hold srcu lock when calling gfn functions
  kvm/ppc/booke64: Disable e6500 support
  kvm/ppc/booke64: Fix AltiVec interrupt numbers and build breakage
  mips/kvm: Use KVM_REG_MIPS and proper size indicators for *_ONE_REG
  kvm: Add definition of KVM_REG_MIPS
  KVM: add kvm_para_available to asm-generic/kvm_para.h
parents 34376a50 7c11c0cc

arch/mips/include/uapi/asm/kvm.h

+39 −42
Original line number Original line Diff line number Diff line
@@ -58,56 +58,53 @@ struct kvm_fpu { 
 *  bits[2..0]   - Register 'sel' index.

 *  bits[2..0]   - Register 'sel' index.

 *  bits[7..3]   - Register 'rd'  index.

 *  bits[7..3]   - Register 'rd'  index.

 *  bits[15..8]  - Must be zero.

 *  bits[15..8]  - Must be zero.

 *  bits[63..16] - 1 -> CP0 registers.

 *  bits[31..16] - 1 -> CP0 registers.

 *  bits[51..32] - Must be zero.

 *  bits[63..52] - As per linux/kvm.h

 *

 *

 * Other sets registers may be added in the future.  Each set would

 * Other sets registers may be added in the future.  Each set would

 * have its own identifier in bits[63..16].

 * have its own identifier in bits[31..16].

 *

 * The addr field of struct kvm_one_reg must point to an aligned

 * 64-bit wide location.  For registers that are narrower than

 * 64-bits, the value is stored in the low order bits of the location,

 * and sign extended to 64-bits.

 *

 *

 * The registers defined in struct kvm_regs are also accessible, the

 * The registers defined in struct kvm_regs are also accessible, the

 * id values for these are below.

 * id values for these are below.

 */

 */





#define KVM_REG_MIPS_R0 0

#define KVM_REG_MIPS_R0 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 0)

#define KVM_REG_MIPS_R1 1

#define KVM_REG_MIPS_R1 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 1)

#define KVM_REG_MIPS_R2 2

#define KVM_REG_MIPS_R2 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 2)

#define KVM_REG_MIPS_R3 3

#define KVM_REG_MIPS_R3 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 3)

#define KVM_REG_MIPS_R4 4

#define KVM_REG_MIPS_R4 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 4)

#define KVM_REG_MIPS_R5 5

#define KVM_REG_MIPS_R5 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 5)

#define KVM_REG_MIPS_R6 6

#define KVM_REG_MIPS_R6 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 6)

#define KVM_REG_MIPS_R7 7

#define KVM_REG_MIPS_R7 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 7)

#define KVM_REG_MIPS_R8 8

#define KVM_REG_MIPS_R8 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 8)

#define KVM_REG_MIPS_R9 9

#define KVM_REG_MIPS_R9 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 9)

#define KVM_REG_MIPS_R10 10

#define KVM_REG_MIPS_R10 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 10)

#define KVM_REG_MIPS_R11 11

#define KVM_REG_MIPS_R11 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 11)

#define KVM_REG_MIPS_R12 12

#define KVM_REG_MIPS_R12 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 12)

#define KVM_REG_MIPS_R13 13

#define KVM_REG_MIPS_R13 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 13)

#define KVM_REG_MIPS_R14 14

#define KVM_REG_MIPS_R14 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 14)

#define KVM_REG_MIPS_R15 15

#define KVM_REG_MIPS_R15 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 15)

#define KVM_REG_MIPS_R16 16

#define KVM_REG_MIPS_R16 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 16)

#define KVM_REG_MIPS_R17 17

#define KVM_REG_MIPS_R17 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 17)

#define KVM_REG_MIPS_R18 18

#define KVM_REG_MIPS_R18 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 18)

#define KVM_REG_MIPS_R19 19

#define KVM_REG_MIPS_R19 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 19)

#define KVM_REG_MIPS_R20 20

#define KVM_REG_MIPS_R20 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 20)

#define KVM_REG_MIPS_R21 21

#define KVM_REG_MIPS_R21 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 21)

#define KVM_REG_MIPS_R22 22

#define KVM_REG_MIPS_R22 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 22)

#define KVM_REG_MIPS_R23 23

#define KVM_REG_MIPS_R23 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 23)

#define KVM_REG_MIPS_R24 24

#define KVM_REG_MIPS_R24 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 24)

#define KVM_REG_MIPS_R25 25

#define KVM_REG_MIPS_R25 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 25)

#define KVM_REG_MIPS_R26 26

#define KVM_REG_MIPS_R26 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 26)

#define KVM_REG_MIPS_R27 27

#define KVM_REG_MIPS_R27 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 27)

#define KVM_REG_MIPS_R28 28

#define KVM_REG_MIPS_R28 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 28)

#define KVM_REG_MIPS_R29 29

#define KVM_REG_MIPS_R29 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 29)

#define KVM_REG_MIPS_R30 30

#define KVM_REG_MIPS_R30 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 30)

#define KVM_REG_MIPS_R31 31

#define KVM_REG_MIPS_R31 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 31)





#define KVM_REG_MIPS_HI 32

#define KVM_REG_MIPS_HI (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 32)

#define KVM_REG_MIPS_LO 33

#define KVM_REG_MIPS_LO (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 33)

#define KVM_REG_MIPS_PC 34

#define KVM_REG_MIPS_PC (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 34)





/*

/*

 * KVM MIPS specific structures and definitions

 * KVM MIPS specific structures and definitions

arch/mips/kvm/kvm_mips.c

+54 −29
Original line number Original line Diff line number Diff line
@@ -485,29 +485,35 @@ kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu, 
	return -ENOIOCTLCMD;

	return -ENOIOCTLCMD;

}

}





#define KVM_REG_MIPS_CP0_INDEX (0x10000 + 8 * 0 + 0)

#define MIPS_CP0_32(_R, _S)					\

#define KVM_REG_MIPS_CP0_ENTRYLO0 (0x10000 + 8 * 2 + 0)

	(KVM_REG_MIPS | KVM_REG_SIZE_U32 | 0x10000 | (8 * (_R) + (_S)))

#define KVM_REG_MIPS_CP0_ENTRYLO1 (0x10000 + 8 * 3 + 0)



#define KVM_REG_MIPS_CP0_CONTEXT (0x10000 + 8 * 4 + 0)

#define MIPS_CP0_64(_R, _S)					\

#define KVM_REG_MIPS_CP0_USERLOCAL (0x10000 + 8 * 4 + 2)

	(KVM_REG_MIPS | KVM_REG_SIZE_U64 | 0x10000 | (8 * (_R) + (_S)))

#define KVM_REG_MIPS_CP0_PAGEMASK (0x10000 + 8 * 5 + 0)



#define KVM_REG_MIPS_CP0_PAGEGRAIN (0x10000 + 8 * 5 + 1)

#define KVM_REG_MIPS_CP0_INDEX		MIPS_CP0_32(0, 0)

#define KVM_REG_MIPS_CP0_WIRED (0x10000 + 8 * 6 + 0)

#define KVM_REG_MIPS_CP0_ENTRYLO0	MIPS_CP0_64(2, 0)

#define KVM_REG_MIPS_CP0_HWRENA (0x10000 + 8 * 7 + 0)

#define KVM_REG_MIPS_CP0_ENTRYLO1	MIPS_CP0_64(3, 0)

#define KVM_REG_MIPS_CP0_BADVADDR (0x10000 + 8 * 8 + 0)

#define KVM_REG_MIPS_CP0_CONTEXT	MIPS_CP0_64(4, 0)

#define KVM_REG_MIPS_CP0_COUNT (0x10000 + 8 * 9 + 0)

#define KVM_REG_MIPS_CP0_USERLOCAL	MIPS_CP0_64(4, 2)

#define KVM_REG_MIPS_CP0_ENTRYHI (0x10000 + 8 * 10 + 0)

#define KVM_REG_MIPS_CP0_PAGEMASK	MIPS_CP0_32(5, 0)

#define KVM_REG_MIPS_CP0_COMPARE (0x10000 + 8 * 11 + 0)

#define KVM_REG_MIPS_CP0_PAGEGRAIN	MIPS_CP0_32(5, 1)

#define KVM_REG_MIPS_CP0_STATUS (0x10000 + 8 * 12 + 0)

#define KVM_REG_MIPS_CP0_WIRED		MIPS_CP0_32(6, 0)

#define KVM_REG_MIPS_CP0_CAUSE (0x10000 + 8 * 13 + 0)

#define KVM_REG_MIPS_CP0_HWRENA		MIPS_CP0_32(7, 0)

#define KVM_REG_MIPS_CP0_EBASE (0x10000 + 8 * 15 + 1)

#define KVM_REG_MIPS_CP0_BADVADDR	MIPS_CP0_64(8, 0)

#define KVM_REG_MIPS_CP0_CONFIG (0x10000 + 8 * 16 + 0)

#define KVM_REG_MIPS_CP0_COUNT		MIPS_CP0_32(9, 0)

#define KVM_REG_MIPS_CP0_CONFIG1 (0x10000 + 8 * 16 + 1)

#define KVM_REG_MIPS_CP0_ENTRYHI	MIPS_CP0_64(10, 0)

#define KVM_REG_MIPS_CP0_CONFIG2 (0x10000 + 8 * 16 + 2)

#define KVM_REG_MIPS_CP0_COMPARE	MIPS_CP0_32(11, 0)

#define KVM_REG_MIPS_CP0_CONFIG3 (0x10000 + 8 * 16 + 3)

#define KVM_REG_MIPS_CP0_STATUS		MIPS_CP0_32(12, 0)

#define KVM_REG_MIPS_CP0_CONFIG7 (0x10000 + 8 * 16 + 7)

#define KVM_REG_MIPS_CP0_CAUSE		MIPS_CP0_32(13, 0)

#define KVM_REG_MIPS_CP0_XCONTEXT (0x10000 + 8 * 20 + 0)

#define KVM_REG_MIPS_CP0_EBASE		MIPS_CP0_64(15, 1)

#define KVM_REG_MIPS_CP0_ERROREPC (0x10000 + 8 * 30 + 0)

#define KVM_REG_MIPS_CP0_CONFIG		MIPS_CP0_32(16, 0)

#define KVM_REG_MIPS_CP0_CONFIG1	MIPS_CP0_32(16, 1)

#define KVM_REG_MIPS_CP0_CONFIG2	MIPS_CP0_32(16, 2)

#define KVM_REG_MIPS_CP0_CONFIG3	MIPS_CP0_32(16, 3)

#define KVM_REG_MIPS_CP0_CONFIG7	MIPS_CP0_32(16, 7)

#define KVM_REG_MIPS_CP0_XCONTEXT	MIPS_CP0_64(20, 0)

#define KVM_REG_MIPS_CP0_ERROREPC	MIPS_CP0_64(30, 0)





static u64 kvm_mips_get_one_regs[] = {

static u64 kvm_mips_get_one_regs[] = {

	KVM_REG_MIPS_R0,

	KVM_REG_MIPS_R0,
@@ -567,8 +573,6 @@ static u64 kvm_mips_get_one_regs[] = { 
static int kvm_mips_get_reg(struct kvm_vcpu *vcpu,

static int kvm_mips_get_reg(struct kvm_vcpu *vcpu,

			    const struct kvm_one_reg *reg)

			    const struct kvm_one_reg *reg)

{

{

	u64 __user *uaddr = (u64 __user *)(long)reg->addr;



	struct mips_coproc *cop0 = vcpu->arch.cop0;

	struct mips_coproc *cop0 = vcpu->arch.cop0;

	s64 v;

	s64 v;
@@ -631,18 +635,39 @@ static int kvm_mips_get_reg(struct kvm_vcpu *vcpu, 
	default:

	default:

		return -EINVAL;

		return -EINVAL;

	}

	}

	return put_user(v, uaddr);

	if ((reg->id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U64) {

		u64 __user *uaddr64 = (u64 __user *)(long)reg->addr;

		return put_user(v, uaddr64);

	} else if ((reg->id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U32) {

		u32 __user *uaddr32 = (u32 __user *)(long)reg->addr;

		u32 v32 = (u32)v;

		return put_user(v32, uaddr32);

	} else {

		return -EINVAL;

	}

}

}





static int kvm_mips_set_reg(struct kvm_vcpu *vcpu,

static int kvm_mips_set_reg(struct kvm_vcpu *vcpu,

			    const struct kvm_one_reg *reg)

			    const struct kvm_one_reg *reg)

{

{

	u64 __user *uaddr = (u64 __user *)(long)reg->addr;

	struct mips_coproc *cop0 = vcpu->arch.cop0;

	struct mips_coproc *cop0 = vcpu->arch.cop0;

	u64 v;

	u64 v;





	if (get_user(v, uaddr) != 0)

	if ((reg->id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U64) {

		u64 __user *uaddr64 = (u64 __user *)(long)reg->addr;



		if (get_user(v, uaddr64) != 0)

			return -EFAULT;

			return -EFAULT;

	} else if ((reg->id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U32) {

		u32 __user *uaddr32 = (u32 __user *)(long)reg->addr;

		s32 v32;



		if (get_user(v32, uaddr32) != 0)

			return -EFAULT;

		v = (s64)v32;

	} else {

		return -EINVAL;

	}





	switch (reg->id) {

	switch (reg->id) {

	case KVM_REG_MIPS_R0:

	case KVM_REG_MIPS_R0:

arch/powerpc/include/asm/kvm_asm.h

+10 −6
Original line number Original line Diff line number Diff line
@@ -54,8 +54,16 @@ 
#define BOOKE_INTERRUPT_DEBUG 15

#define BOOKE_INTERRUPT_DEBUG 15





/* E500 */

/* E500 */

#define BOOKE_INTERRUPT_SPE_UNAVAIL 32

#define BOOKE_INTERRUPT_SPE_ALTIVEC_UNAVAIL 32

#define BOOKE_INTERRUPT_SPE_FP_DATA 33

#define BOOKE_INTERRUPT_SPE_FP_DATA_ALTIVEC_ASSIST 33

/*

 * TODO: Unify 32-bit and 64-bit kernel exception handlers to use same defines

 */

#define BOOKE_INTERRUPT_SPE_UNAVAIL BOOKE_INTERRUPT_SPE_ALTIVEC_UNAVAIL

#define BOOKE_INTERRUPT_SPE_FP_DATA BOOKE_INTERRUPT_SPE_FP_DATA_ALTIVEC_ASSIST

#define BOOKE_INTERRUPT_ALTIVEC_UNAVAIL BOOKE_INTERRUPT_SPE_ALTIVEC_UNAVAIL

#define BOOKE_INTERRUPT_ALTIVEC_ASSIST \

				BOOKE_INTERRUPT_SPE_FP_DATA_ALTIVEC_ASSIST

#define BOOKE_INTERRUPT_SPE_FP_ROUND 34

#define BOOKE_INTERRUPT_SPE_FP_ROUND 34

#define BOOKE_INTERRUPT_PERFORMANCE_MONITOR 35

#define BOOKE_INTERRUPT_PERFORMANCE_MONITOR 35

#define BOOKE_INTERRUPT_DOORBELL 36

#define BOOKE_INTERRUPT_DOORBELL 36
@@ -67,10 +75,6 @@ 
#define BOOKE_INTERRUPT_HV_SYSCALL 40

#define BOOKE_INTERRUPT_HV_SYSCALL 40

#define BOOKE_INTERRUPT_HV_PRIV 41

#define BOOKE_INTERRUPT_HV_PRIV 41





/* altivec */

#define BOOKE_INTERRUPT_ALTIVEC_UNAVAIL 42

#define BOOKE_INTERRUPT_ALTIVEC_ASSIST 43



/* book3s */

/* book3s */





#define BOOK3S_INTERRUPT_SYSTEM_RESET	0x100

#define BOOK3S_INTERRUPT_SYSTEM_RESET	0x100

arch/powerpc/kvm/44x_tlb.c

+5 −0
Original line number Original line Diff line number Diff line
@@ -441,6 +441,7 @@ int kvmppc_44x_emul_tlbwe(struct kvm_vcpu *vcpu, u8 ra, u8 rs, u8 ws) 
	struct kvmppc_vcpu_44x *vcpu_44x = to_44x(vcpu);

	struct kvmppc_vcpu_44x *vcpu_44x = to_44x(vcpu);

	struct kvmppc_44x_tlbe *tlbe;

	struct kvmppc_44x_tlbe *tlbe;

	unsigned int gtlb_index;

	unsigned int gtlb_index;

	int idx;





	gtlb_index = kvmppc_get_gpr(vcpu, ra);

	gtlb_index = kvmppc_get_gpr(vcpu, ra);

	if (gtlb_index >= KVM44x_GUEST_TLB_SIZE) {

	if (gtlb_index >= KVM44x_GUEST_TLB_SIZE) {
@@ -473,6 +474,8 @@ int kvmppc_44x_emul_tlbwe(struct kvm_vcpu *vcpu, u8 ra, u8 rs, u8 ws) 
		return EMULATE_FAIL;

		return EMULATE_FAIL;

	}

	}





	idx = srcu_read_lock(&vcpu->kvm->srcu);



	if (tlbe_is_host_safe(vcpu, tlbe)) {

	if (tlbe_is_host_safe(vcpu, tlbe)) {

		gva_t eaddr;

		gva_t eaddr;

		gpa_t gpaddr;

		gpa_t gpaddr;
@@ -489,6 +492,8 @@ int kvmppc_44x_emul_tlbwe(struct kvm_vcpu *vcpu, u8 ra, u8 rs, u8 ws) 
		kvmppc_mmu_map(vcpu, eaddr, gpaddr, gtlb_index);

		kvmppc_mmu_map(vcpu, eaddr, gpaddr, gtlb_index);

	}

	}





	srcu_read_unlock(&vcpu->kvm->srcu, idx);



	trace_kvm_gtlb_write(gtlb_index, tlbe->tid, tlbe->word0, tlbe->word1,

	trace_kvm_gtlb_write(gtlb_index, tlbe->tid, tlbe->word0, tlbe->word1,

			     tlbe->word2);

			     tlbe->word2);

arch/powerpc/kvm/booke.c

+18 −0
Original line number Original line Diff line number Diff line
@@ -832,6 +832,18 @@ int kvmppc_handle_exit(struct kvm_run *run, struct kvm_vcpu *vcpu, 
{

{

	int r = RESUME_HOST;

	int r = RESUME_HOST;

	int s;

	int s;

	int idx;



#ifdef CONFIG_PPC64

	WARN_ON(local_paca->irq_happened != 0);

#endif



	/*

	 * We enter with interrupts disabled in hardware, but

	 * we need to call hard_irq_disable anyway to ensure that

	 * the software state is kept in sync.

	 */

	hard_irq_disable();





	/* update before a new last_exit_type is rewritten */

	/* update before a new last_exit_type is rewritten */

	kvmppc_update_timing_stats(vcpu);

	kvmppc_update_timing_stats(vcpu);
@@ -1053,6 +1065,8 @@ int kvmppc_handle_exit(struct kvm_run *run, struct kvm_vcpu *vcpu, 
			break;

			break;

		}

		}





		idx = srcu_read_lock(&vcpu->kvm->srcu);



		gpaddr = kvmppc_mmu_xlate(vcpu, gtlb_index, eaddr);

		gpaddr = kvmppc_mmu_xlate(vcpu, gtlb_index, eaddr);

		gfn = gpaddr >> PAGE_SHIFT;

		gfn = gpaddr >> PAGE_SHIFT;
@@ -1075,6 +1089,7 @@ int kvmppc_handle_exit(struct kvm_run *run, struct kvm_vcpu *vcpu, 
			kvmppc_account_exit(vcpu, MMIO_EXITS);

			kvmppc_account_exit(vcpu, MMIO_EXITS);

		}

		}





		srcu_read_unlock(&vcpu->kvm->srcu, idx);

		break;

		break;

	}

	}
@@ -1098,6 +1113,8 @@ int kvmppc_handle_exit(struct kvm_run *run, struct kvm_vcpu *vcpu, 




		kvmppc_account_exit(vcpu, ITLB_VIRT_MISS_EXITS);

		kvmppc_account_exit(vcpu, ITLB_VIRT_MISS_EXITS);





		idx = srcu_read_lock(&vcpu->kvm->srcu);



		gpaddr = kvmppc_mmu_xlate(vcpu, gtlb_index, eaddr);

		gpaddr = kvmppc_mmu_xlate(vcpu, gtlb_index, eaddr);

		gfn = gpaddr >> PAGE_SHIFT;

		gfn = gpaddr >> PAGE_SHIFT;
@@ -1114,6 +1131,7 @@ int kvmppc_handle_exit(struct kvm_run *run, struct kvm_vcpu *vcpu, 
			kvmppc_booke_queue_irqprio(vcpu, BOOKE_IRQPRIO_MACHINE_CHECK);

			kvmppc_booke_queue_irqprio(vcpu, BOOKE_IRQPRIO_MACHINE_CHECK);

		}

		}





		srcu_read_unlock(&vcpu->kvm->srcu, idx);

		break;

		break;

	}

	}

CRA Git | Maintained and supported by SUSTech CRA and CCSE