Commit aefa794e authored Jun 15, 2017 by Antoine Ténart Committed by Herbert Xu Jun 20, 2017

crypto: inside-secure - fix the ring wr_cache offset



The EIP197_HIA_xDR_CFG_WR_CACHE macro was defined to use an offset of
23, which is wrong as it's actually 25. Fix this.

Reported-by: Igal Liberman <igall@marvell.com>
Signed-off-by: Antoine Tenart <antoine.tenart@free-electrons.com>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>

parent aed3731e

drivers/crypto/inside-secure/safexcel.h

+1 −1

Original line number	Diff line number	Diff line
		@@ -99,7 +99,7 @@
		#define EIP197_HIA_xDR_WR_RES_BUF BIT(22)
		#define EIP197_HIA_xDR_WR_CTRL_BUG BIT(23)
		#define EIP197_HIA_xDR_WR_OWN_BUF BIT(24)
		#define EIP197_HIA_xDR_CFG_WR_CACHE(n) (((n) & 0x7) << 23)
		#define EIP197_HIA_xDR_CFG_WR_CACHE(n) (((n) & 0x7) << 25)
		#define EIP197_HIA_xDR_CFG_RD_CACHE(n) (((n) & 0x7) << 29)

		/* EIP197_HIA_CDR_THRESH */

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