Commit aed4d4c6 authored Aug 26, 2020 by Tariq Toukan Committed by David S. Miller Aug 26, 2020

net/mlx4_en: RX, Add a prefetch command for small L1_CACHE_BYTES



A single cacheline might not contain the packet header for
small L1_CACHE_BYTES values.
Use net_prefetch() as it issues an additional prefetch
in this case.

Signed-off-by: Tariq Toukan <tariqt@mellanox.com>
Reviewed-by: Saeed Mahameed <saeedm@mellanox.com>
Signed-off-by: David S. Miller <davem@davemloft.net>

parent e20f0dbf

drivers/net/ethernet/mellanox/mlx4/en_rx.c

+1 −1

Original line number	Diff line number	Diff line
		@@ -705,7 +705,7 @@ int mlx4_en_process_rx_cq(struct net_device dev, struct mlx4_en_cq cq, int bud

		frags = ring->rx_info + (index << priv->log_rx_info);
		va = page_address(frags[0].page) + frags[0].page_offset;
		prefetchw(va);
		net_prefetchw(va);
		/*
		* make sure we read the CQE after we read the ownership bit
		*/

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