Commit aeaf6a4b authored by Sudeep Holla's avatar Sudeep Holla Committed by Rafael J. Wysocki
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dt-bindings: cpufreq: remove stale arm_big_little_dt entry



Most of the ARM platforms used v2 OPP bindings to support big-little
configurations. This arm_big_little_dt binding is incomplete and was
never used.

Commit f174e49e (cpufreq: remove unused arm_big_little_dt driver)
removed the driver supporting this binding, but the binding was left
unnoticed, so let's get rid of it now.

Fixes: f174e49e (cpufreq: remove unused arm_big_little_dt driver)
Signed-off-by: default avatarSudeep Holla <sudeep.holla@arm.com>
Acked-by: default avatarViresh Kumar <viresh.kumar@linaro.org>
Signed-off-by: default avatarRafael J. Wysocki <rafael.j.wysocki@intel.com>
parent e531efa1
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Generic ARM big LITTLE cpufreq driver's DT glue
-----------------------------------------------

This is DT specific glue layer for generic cpufreq driver for big LITTLE
systems.

Both required and optional properties listed below must be defined
under node /cpus/cpu@x. Where x is the first cpu inside a cluster.

FIXME: Cpus should boot in the order specified in DT and all cpus for a cluster
must be present contiguously. Generic DT driver will check only node 'x' for
cpu:x.

Required properties:
- operating-points: Refer to Documentation/devicetree/bindings/opp/opp.txt
  for details

Optional properties:
- clock-latency: Specify the possible maximum transition latency for clock,
  in unit of nanoseconds.

Examples:

cpus {
	#address-cells = <1>;
	#size-cells = <0>;

	cpu@0 {
		compatible = "arm,cortex-a15";
		reg = <0>;
		next-level-cache = <&L2>;
		operating-points = <
			/* kHz    uV */
			792000  1100000
			396000  950000
			198000  850000
		>;
		clock-latency = <61036>; /* two CLK32 periods */
	};

	cpu@1 {
		compatible = "arm,cortex-a15";
		reg = <1>;
		next-level-cache = <&L2>;
	};

	cpu@100 {
		compatible = "arm,cortex-a7";
		reg = <100>;
		next-level-cache = <&L2>;
		operating-points = <
			/* kHz    uV */
			792000  950000
			396000  750000
			198000  450000
		>;
		clock-latency = <61036>; /* two CLK32 periods */
	};

	cpu@101 {
		compatible = "arm,cortex-a7";
		reg = <101>;
		next-level-cache = <&L2>;
	};
};