Commit aeab9eda authored by Gao, Fred's avatar Gao, Fred Committed by Zhenyu Wang
Browse files

drm/i915/gvt: Refine non privilege register address calucation 



The BitField of non privilege register address is only from bit 2 to 25.

v2: use REG_GENMASK instead. (Zhenyu)

Signed-off-by: default avatarGao, Fred <fred.gao@intel.com>
Reviewed-by: default avatarZhenyu Wang <zhenyuw@linux.intel.com>
Signed-off-by: default avatarZhenyu Wang <zhenyuw@linux.intel.com>
parent 83faaf07

drivers/gpu/drm/i915/gvt/handlers.c

+2 −2
Original line number Original line Diff line number Diff line
@@ -508,7 +508,7 @@ static inline bool in_whitelist(unsigned int reg) 
static int force_nonpriv_write(struct intel_vgpu *vgpu,

static int force_nonpriv_write(struct intel_vgpu *vgpu,

	unsigned int offset, void *p_data, unsigned int bytes)

	unsigned int offset, void *p_data, unsigned int bytes)

{

{

	u32 reg_nonpriv = *(u32 *)p_data;

	u32 reg_nonpriv = (*(u32 *)p_data) & REG_GENMASK(25, 2);

	int ring_id = intel_gvt_render_mmio_to_ring_id(vgpu->gvt, offset);

	int ring_id = intel_gvt_render_mmio_to_ring_id(vgpu->gvt, offset);

	u32 ring_base;

	u32 ring_base;

	struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;

	struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
@@ -528,7 +528,7 @@ static int force_nonpriv_write(struct intel_vgpu *vgpu, 
			bytes);

			bytes);

	} else

	} else

		gvt_err("vgpu(%d) Invalid FORCE_NONPRIV write %x at offset %x\n",

		gvt_err("vgpu(%d) Invalid FORCE_NONPRIV write %x at offset %x\n",

			vgpu->id, reg_nonpriv, offset);

			vgpu->id, *(u32 *)p_data, offset);





	return 0;

	return 0;

}

}

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