Commit aea7687e authored by Hauke Mehrtens's avatar Hauke Mehrtens Committed by Miquel Raynal
Browse files

mtd: spinand: gigadevice: Add QE Bit 



The following GigaDevice chips have the QE BIT in the feature flags, I
checked the datasheets, but did not try this.
* GD5F1GQ4xExxG
* GD5F1GQ4xFxxG
* GD5F1GQ4UAYIG
* GD5F4GQ4UAYIG

The Quad operations like 0xEB mention that the QE bit has to be set.

Fixes: c93c6132 ("mtd: spinand: add support for GigaDevice GD5FxGQ4xA")
Signed-off-by: default avatarHauke Mehrtens <hauke@hauke-m.de>
Tested-by: default avatarChuanhong Guo <gch981213@gmail.com>
Signed-off-by: default avatarMiquel Raynal <miquel.raynal@bootlin.com>
Link: https://lore.kernel.org/linux-mtd/20200820165121.3192-3-hauke@hauke-m.de
parent 6387ad9c

drivers/mtd/nand/spi/gigadevice.c

+5 −5
Original line number Diff line number Diff line
@@ -202,7 +202,7 @@ static const struct spinand_info gigadevice_spinand_table[] = { 
		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,

					      &write_cache_variants,

					      &update_cache_variants),

		     0,

		     SPINAND_HAS_QE_BIT,

		     SPINAND_ECCINFO(&gd5fxgq4xa_ooblayout,

				     gd5fxgq4xa_ecc_get_status)),

	SPINAND_INFO("GD5F2GQ4xA",
@@ -212,7 +212,7 @@ static const struct spinand_info gigadevice_spinand_table[] = { 
		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,

					      &write_cache_variants,

					      &update_cache_variants),

		     0,

		     SPINAND_HAS_QE_BIT,

		     SPINAND_ECCINFO(&gd5fxgq4xa_ooblayout,

				     gd5fxgq4xa_ecc_get_status)),

	SPINAND_INFO("GD5F4GQ4xA",
@@ -222,7 +222,7 @@ static const struct spinand_info gigadevice_spinand_table[] = { 
		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,

					      &write_cache_variants,

					      &update_cache_variants),

		     0,

		     SPINAND_HAS_QE_BIT,

		     SPINAND_ECCINFO(&gd5fxgq4xa_ooblayout,

				     gd5fxgq4xa_ecc_get_status)),

	SPINAND_INFO("GD5F1GQ4UExxG",
@@ -232,7 +232,7 @@ static const struct spinand_info gigadevice_spinand_table[] = { 
		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,

					      &write_cache_variants,

					      &update_cache_variants),

		     0,

		     SPINAND_HAS_QE_BIT,

		     SPINAND_ECCINFO(&gd5fxgq4_variant2_ooblayout,

				     gd5fxgq4uexxg_ecc_get_status)),

	SPINAND_INFO("GD5F1GQ4UFxxG",
@@ -242,7 +242,7 @@ static const struct spinand_info gigadevice_spinand_table[] = { 
		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants_f,

					      &write_cache_variants,

					      &update_cache_variants),

		     0,

		     SPINAND_HAS_QE_BIT,

		     SPINAND_ECCINFO(&gd5fxgq4_variant2_ooblayout,

				     gd5fxgq4ufxxg_ecc_get_status)),

};

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