Commit aea0089a authored by Geert Uytterhoeven's avatar Geert Uytterhoeven Committed by Simon Horman
Browse files

ARM: dts: r8a7790: Add clocks for CA7 CPU cores 



Currently only the CPU cores in the CA15 cluster have clocks properties.
Add the missing clocks properties for the CPU cores in the CA7 cluster
to fix this.

Signed-off-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
Tested-by: default avatarSimon Horman <horms+renesas@verge.net.au>
Signed-off-by: default avatarSimon Horman <horms+renesas@verge.net.au>
parent aa4c2fdf

arch/arm/boot/dts/r8a7790.dtsi

+4 −0
Original line number Diff line number Diff line
@@ -105,6 +105,7 @@ 
			compatible = "arm,cortex-a7";

			reg = <0x100>;

			clock-frequency = <780000000>;

			clocks = <&cpg CPG_CORE R8A7790_CLK_Z2>;

			power-domains = <&sysc R8A7790_PD_CA7_CPU0>;

			next-level-cache = <&L2_CA7>;

			capacity-dmips-mhz = <539>;
@@ -115,6 +116,7 @@ 
			compatible = "arm,cortex-a7";

			reg = <0x101>;

			clock-frequency = <780000000>;

			clocks = <&cpg CPG_CORE R8A7790_CLK_Z2>;

			power-domains = <&sysc R8A7790_PD_CA7_CPU1>;

			next-level-cache = <&L2_CA7>;

			capacity-dmips-mhz = <539>;
@@ -125,6 +127,7 @@ 
			compatible = "arm,cortex-a7";

			reg = <0x102>;

			clock-frequency = <780000000>;

			clocks = <&cpg CPG_CORE R8A7790_CLK_Z2>;

			power-domains = <&sysc R8A7790_PD_CA7_CPU2>;

			next-level-cache = <&L2_CA7>;

			capacity-dmips-mhz = <539>;
@@ -135,6 +138,7 @@ 
			compatible = "arm,cortex-a7";

			reg = <0x103>;

			clock-frequency = <780000000>;

			clocks = <&cpg CPG_CORE R8A7790_CLK_Z2>;

			power-domains = <&sysc R8A7790_PD_CA7_CPU3>;

			next-level-cache = <&L2_CA7>;

			capacity-dmips-mhz = <539>;

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