Commit ae8779e1 authored by Eugen Hristev's avatar Eugen Hristev Committed by Greg Kroah-Hartman
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staging: dt-bindings: wilc1000: add optional rtc_clk property

parent 77b0a841
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+7 −1
Original line number Diff line number Diff line
@@ -10,7 +10,9 @@ Required properties:

Optional:
- bus-width	:	Number of data lines wired up the slot. Default 1 bit.

- rtc_clk	:	Clock connected on the rtc clock line. Must be assigned
			a frequency with assigned-clocks property, and must be
			connected to a clock provider.

Examples:
mmc1: mmc@fc000000 {
@@ -24,6 +26,10 @@ mmc1: mmc@fc000000 {
		wilc_sdio@0 {
			compatible = "microchip,wilc1000-sdio";
			irq-gpios = <&pioC 27 0>;
			clocks = <&pck1>;
			clock-names = "rtc_clk";
			assigned-clocks = <&pck1>;
			assigned-clock-rates = <32768>;
			status = "okay";
			reg = <0>;
			bus-width = <4>;
+8 −0
Original line number Diff line number Diff line
@@ -9,6 +9,10 @@ Required properties:
- reg			: Chip select address of device
- irq-gpios		: Connect to a host IRQ

Optional:
- rtc_clk	:	Clock connected on the rtc clock line. Must be assigned
			a frequency with assigned-clocks property, and must be
			connected to a clock provider.

Examples:

@@ -21,6 +25,10 @@ spi1: spi@fc018000 {
			spi-max-frequency = <48000000>;
			reg = <0>;
			irq-gpios = <&pioC 27 0>;
			clocks = <&pck1>;
			clock-names = "rtc_clk";
			assigned-clocks = <&pck1>;
			assigned-clock-rates = <32768>;
			status = "okay";
		};
};