Commit ae75d84f authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge branch 'merge' of git://git.kernel.org/pub/scm/linux/kernel/git/benh/powerpc 

Pull powerpc fixes from Benjamin Herrenschmidt:
 "This is purely regressions (though not all recent ones) or stable
  material"

* 'merge' of git://git.kernel.org/pub/scm/linux/kernel/git/benh/powerpc:
  powerpc: Partial revert of "Context switch more PMU related SPRs"
  powerpc/perf: Fix deadlock caused by calling printk() in PMU exception
  powerpc/hw_breakpoints: Add DABRX cpu feature to fix 32-bit regression
  powerpc/power8: Update denormalization handler
  powerpc/pseries: Simplify denormalization handler
  powerpc/power8: Fix oprofile and perf
  powerpc/eeh: Don't check RTAS token to get PE addr
  powerpc/pci: Check the bus address instead of resource address in pcibios_fixup_resources
parents 0b52a3c8 b11ae951

arch/powerpc/include/asm/cputable.h

+10 −7
Original line number Diff line number Diff line
@@ -176,6 +176,7 @@ extern const char *powerpc_base_platform; 
#define CPU_FTR_CFAR			LONG_ASM_CONST(0x0100000000000000)

#define	CPU_FTR_HAS_PPR			LONG_ASM_CONST(0x0200000000000000)

#define CPU_FTR_DAWR			LONG_ASM_CONST(0x0400000000000000)

#define CPU_FTR_DABRX			LONG_ASM_CONST(0x0800000000000000)



#ifndef __ASSEMBLY__
@@ -394,19 +395,20 @@ extern const char *powerpc_base_platform; 
	    CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | CPU_FTR_ARCH_201 | \

	    CPU_FTR_ALTIVEC_COMP | CPU_FTR_CAN_NAP | CPU_FTR_MMCRA | \

	    CPU_FTR_CP_USE_DCBTZ | CPU_FTR_STCX_CHECKS_ADDRESS | \

	    CPU_FTR_HVMODE)

	    CPU_FTR_HVMODE | CPU_FTR_DABRX)

#define CPU_FTRS_POWER5	(CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \

	    CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \

	    CPU_FTR_MMCRA | CPU_FTR_SMT | \

	    CPU_FTR_COHERENT_ICACHE | CPU_FTR_PURR | \

	    CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB)

	    CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB | CPU_FTR_DABRX)

#define CPU_FTRS_POWER6 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \

	    CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \

	    CPU_FTR_MMCRA | CPU_FTR_SMT | \

	    CPU_FTR_COHERENT_ICACHE | \

	    CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \

	    CPU_FTR_DSCR | CPU_FTR_UNALIGNED_LD_STD | \

	    CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB | CPU_FTR_CFAR)

	    CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB | CPU_FTR_CFAR | \

	    CPU_FTR_DABRX)

#define CPU_FTRS_POWER7 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \

	    CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | CPU_FTR_ARCH_206 |\

	    CPU_FTR_MMCRA | CPU_FTR_SMT | \
@@ -415,7 +417,7 @@ extern const char *powerpc_base_platform; 
	    CPU_FTR_DSCR | CPU_FTR_SAO  | CPU_FTR_ASYM_SMT | \

	    CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB | CPU_FTR_POPCNTD | \

	    CPU_FTR_ICSWX | CPU_FTR_CFAR | CPU_FTR_HVMODE | \

	    CPU_FTR_VMX_COPY | CPU_FTR_HAS_PPR)

	    CPU_FTR_VMX_COPY | CPU_FTR_HAS_PPR | CPU_FTR_DABRX)

#define CPU_FTRS_POWER8 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \

	    CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | CPU_FTR_ARCH_206 |\

	    CPU_FTR_MMCRA | CPU_FTR_SMT | \
@@ -430,14 +432,15 @@ extern const char *powerpc_base_platform; 
	    CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \

	    CPU_FTR_ALTIVEC_COMP | CPU_FTR_MMCRA | CPU_FTR_SMT | \

	    CPU_FTR_PAUSE_ZERO  | CPU_FTR_CELL_TB_BUG | CPU_FTR_CP_USE_DCBTZ | \

	    CPU_FTR_UNALIGNED_LD_STD)

	    CPU_FTR_UNALIGNED_LD_STD | CPU_FTR_DABRX)

#define CPU_FTRS_PA6T (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \

	    CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_ALTIVEC_COMP | \

	    CPU_FTR_PURR | CPU_FTR_REAL_LE)

	    CPU_FTR_PURR | CPU_FTR_REAL_LE | CPU_FTR_DABRX)

#define CPU_FTRS_COMPATIBLE	(CPU_FTR_USE_TB | CPU_FTR_PPCAS_ARCH_V2)



#define CPU_FTRS_A2 (CPU_FTR_USE_TB | CPU_FTR_SMT | CPU_FTR_DBELL | \

		     CPU_FTR_NOEXECUTE | CPU_FTR_NODSISRALIGN | CPU_FTR_ICSWX)

		     CPU_FTR_NOEXECUTE | CPU_FTR_NODSISRALIGN | \

		     CPU_FTR_ICSWX | CPU_FTR_DABRX )



#ifdef __powerpc64__

#ifdef CONFIG_PPC_BOOK3E

arch/powerpc/kernel/cputable.c

+4 −4
Original line number Diff line number Diff line
@@ -452,8 +452,8 @@ static struct cpu_spec __initdata cpu_specs[] = { 
		.mmu_features		= MMU_FTRS_POWER8,

		.icache_bsize		= 128,

		.dcache_bsize		= 128,

		.oprofile_type		= PPC_OPROFILE_POWER4,

		.oprofile_cpu_type	= 0,

		.oprofile_type		= PPC_OPROFILE_INVALID,

		.oprofile_cpu_type	= "ppc64/ibm-compat-v1",

		.cpu_setup		= __setup_cpu_power8,

		.cpu_restore		= __restore_cpu_power8,

		.platform		= "power8",
@@ -506,8 +506,8 @@ static struct cpu_spec __initdata cpu_specs[] = { 
		.dcache_bsize		= 128,

		.num_pmcs		= 6,

		.pmc_type		= PPC_PMC_IBM,

		.oprofile_cpu_type	= 0,

		.oprofile_type		= PPC_OPROFILE_POWER4,

		.oprofile_cpu_type	= "ppc64/power8",

		.oprofile_type		= PPC_OPROFILE_INVALID,

		.cpu_setup		= __setup_cpu_power8,

		.cpu_restore		= __restore_cpu_power8,

		.platform		= "power8",

arch/powerpc/kernel/entry_64.S

+0 −28
Original line number Diff line number Diff line
@@ -465,20 +465,6 @@ BEGIN_FTR_SECTION 
	std	r0, THREAD_EBBHR(r3)

	mfspr	r0, SPRN_EBBRR

	std	r0, THREAD_EBBRR(r3)



	/* PMU registers made user read/(write) by EBB */

	mfspr	r0, SPRN_SIAR

	std	r0, THREAD_SIAR(r3)

	mfspr	r0, SPRN_SDAR

	std	r0, THREAD_SDAR(r3)

	mfspr	r0, SPRN_SIER

	std	r0, THREAD_SIER(r3)

	mfspr	r0, SPRN_MMCR0

	std	r0, THREAD_MMCR0(r3)

	mfspr	r0, SPRN_MMCR2

	std	r0, THREAD_MMCR2(r3)

	mfspr	r0, SPRN_MMCRA

	std	r0, THREAD_MMCRA(r3)

END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)

#endif
@@ -581,20 +567,6 @@ BEGIN_FTR_SECTION 
	ld	r0, THREAD_EBBRR(r4)

	mtspr	SPRN_EBBRR, r0



	/* PMU registers made user read/(write) by EBB */

	ld	r0, THREAD_SIAR(r4)

	mtspr	SPRN_SIAR, r0

	ld	r0, THREAD_SDAR(r4)

	mtspr	SPRN_SDAR, r0

	ld	r0, THREAD_SIER(r4)

	mtspr	SPRN_SIER, r0

	ld	r0, THREAD_MMCR0(r4)

	mtspr	SPRN_MMCR0, r0

	ld	r0, THREAD_MMCR2(r4)

	mtspr	SPRN_MMCR2, r0

	ld	r0, THREAD_MMCRA(r4)

	mtspr	SPRN_MMCRA, r0



	ld	r0,THREAD_TAR(r4)

	mtspr	SPRN_TAR,r0

END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)

arch/powerpc/kernel/exceptions-64s.S

+26 −64
Original line number Diff line number Diff line
@@ -454,38 +454,14 @@ BEGIN_FTR_SECTION 
	xori	r10,r10,(MSR_FE0|MSR_FE1)

	mtmsrd	r10

	sync

	fmr	0,0

	fmr	1,1

	fmr	2,2

	fmr	3,3

	fmr	4,4

	fmr	5,5

	fmr	6,6

	fmr	7,7

	fmr	8,8

	fmr	9,9

	fmr	10,10

	fmr	11,11

	fmr	12,12

	fmr	13,13

	fmr	14,14

	fmr	15,15

	fmr	16,16

	fmr	17,17

	fmr	18,18

	fmr	19,19

	fmr	20,20

	fmr	21,21

	fmr	22,22

	fmr	23,23

	fmr	24,24

	fmr	25,25

	fmr	26,26

	fmr	27,27

	fmr	28,28

	fmr	29,29

	fmr	30,30

	fmr	31,31



#define FMR2(n)  fmr (n), (n) ; fmr n+1, n+1

#define FMR4(n)  FMR2(n) ; FMR2(n+2)

#define FMR8(n)  FMR4(n) ; FMR4(n+4)

#define FMR16(n) FMR8(n) ; FMR8(n+8)

#define FMR32(n) FMR16(n) ; FMR16(n+16)

	FMR32(0)



FTR_SECTION_ELSE

/*

 * To denormalise we need to move a copy of the register to itself.
@@ -495,39 +471,25 @@ FTR_SECTION_ELSE 
	oris	r10,r10,MSR_VSX@h

	mtmsrd	r10

	sync

	XVCPSGNDP(0,0,0)

	XVCPSGNDP(1,1,1)

	XVCPSGNDP(2,2,2)

	XVCPSGNDP(3,3,3)

	XVCPSGNDP(4,4,4)

	XVCPSGNDP(5,5,5)

	XVCPSGNDP(6,6,6)

	XVCPSGNDP(7,7,7)

	XVCPSGNDP(8,8,8)

	XVCPSGNDP(9,9,9)

	XVCPSGNDP(10,10,10)

	XVCPSGNDP(11,11,11)

	XVCPSGNDP(12,12,12)

	XVCPSGNDP(13,13,13)

	XVCPSGNDP(14,14,14)

	XVCPSGNDP(15,15,15)

	XVCPSGNDP(16,16,16)

	XVCPSGNDP(17,17,17)

	XVCPSGNDP(18,18,18)

	XVCPSGNDP(19,19,19)

	XVCPSGNDP(20,20,20)

	XVCPSGNDP(21,21,21)

	XVCPSGNDP(22,22,22)

	XVCPSGNDP(23,23,23)

	XVCPSGNDP(24,24,24)

	XVCPSGNDP(25,25,25)

	XVCPSGNDP(26,26,26)

	XVCPSGNDP(27,27,27)

	XVCPSGNDP(28,28,28)

	XVCPSGNDP(29,29,29)

	XVCPSGNDP(30,30,30)

	XVCPSGNDP(31,31,31)



#define XVCPSGNDP2(n) XVCPSGNDP(n,n,n) ; XVCPSGNDP(n+1,n+1,n+1)

#define XVCPSGNDP4(n) XVCPSGNDP2(n) ; XVCPSGNDP2(n+2)

#define XVCPSGNDP8(n) XVCPSGNDP4(n) ; XVCPSGNDP4(n+4)

#define XVCPSGNDP16(n) XVCPSGNDP8(n) ; XVCPSGNDP8(n+8)

#define XVCPSGNDP32(n) XVCPSGNDP16(n) ; XVCPSGNDP16(n+16)

	XVCPSGNDP32(0)



ALT_FTR_SECTION_END_IFCLR(CPU_FTR_ARCH_206)



BEGIN_FTR_SECTION

	b	denorm_done

END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_207S)

/*

 * To denormalise we need to move a copy of the register to itself.

 * For POWER8 we need to do that for all 64 VSX registers

 */

	XVCPSGNDP32(32)

denorm_done:

	mtspr	SPRN_HSRR0,r11

	mtcrf	0x80,r9

	ld	r9,PACA_EXGEN+EX_R9(r13)

arch/powerpc/kernel/pci-common.c

+3 −1
Original line number Diff line number Diff line
@@ -827,6 +827,7 @@ static void pcibios_fixup_resources(struct pci_dev *dev) 
	}

	for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {

		struct resource *res = dev->resource + i;

		struct pci_bus_region reg;

		if (!res->flags)

			continue;
@@ -835,8 +836,9 @@ static void pcibios_fixup_resources(struct pci_dev *dev) 
		 * at 0 as unset as well, except if PCI_PROBE_ONLY is also set

		 * since in that case, we don't want to re-assign anything

		 */

		pcibios_resource_to_bus(dev, &reg, res);

		if (pci_has_flag(PCI_REASSIGN_ALL_RSRC) ||

		    (res->start == 0 && !pci_has_flag(PCI_PROBE_ONLY))) {

		    (reg.start == 0 && !pci_has_flag(PCI_PROBE_ONLY))) {

			/* Only print message if not re-assigning */

			if (!pci_has_flag(PCI_REASSIGN_ALL_RSRC))

				pr_debug("PCI:%s Resource %d %016llx-%016llx [%x] "

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