Commit ae453006 authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge branch 'etnaviv/next' of https://git.pengutronix.de/git/lst/linux into drm-next 



Most importantly per-process address spaces on GPUs that are capable of
providing proper isolation has finished baking. This is the base for
our softpin implementation, which allows us to support the texture
descriptor buffers used by GC7000 series GPUs without a major UAPI
extension/rework.

Shortlog of notable changes:
- code cleanup from Fabio
- fix performance counters on GC880 and GC2000 GPUs from Christian
- drmP.h header removal from Sam
- per process address space support on MMUv2 GPUs from me
- softpin support from me

Signed-off-by: default avatarDave Airlie <airlied@redhat.com>
From: Lucas Stach <l.stach@pengutronix.de>
Link: https://patchwork.freedesktop.org/patch/msgid/1565946875.2641.73.camel@pengutronix.de
parents c011b93c 088880dd

drivers/gpu/drm/etnaviv/etnaviv_buffer.c

+70 −23
Original line number Diff line number Diff line
@@ -3,6 +3,8 @@ 
 * Copyright (C) 2014-2018 Etnaviv Project

 */



#include <drm/drm_drv.h>



#include "etnaviv_cmdbuf.h"

#include "etnaviv_gpu.h"

#include "etnaviv_gem.h"
@@ -116,7 +118,9 @@ static void etnaviv_buffer_dump(struct etnaviv_gpu *gpu, 
	u32 *ptr = buf->vaddr + off;



	dev_info(gpu->dev, "virt %p phys 0x%08x free 0x%08x\n",

			ptr, etnaviv_cmdbuf_get_va(buf) + off, size - len * 4 - off);

			ptr, etnaviv_cmdbuf_get_va(buf,

			&gpu->mmu_context->cmdbuf_mapping) +

			off, size - len * 4 - off);



	print_hex_dump(KERN_INFO, "cmd ", DUMP_PREFIX_OFFSET, 16, 4,

			ptr, len * 4, 0);
@@ -149,7 +153,9 @@ static u32 etnaviv_buffer_reserve(struct etnaviv_gpu *gpu, 
	if (buffer->user_size + cmd_dwords * sizeof(u64) > buffer->size)

		buffer->user_size = 0;



	return etnaviv_cmdbuf_get_va(buffer) + buffer->user_size;

	return etnaviv_cmdbuf_get_va(buffer,

				     &gpu->mmu_context->cmdbuf_mapping) +

	       buffer->user_size;

}



u16 etnaviv_buffer_init(struct etnaviv_gpu *gpu)
@@ -162,8 +168,9 @@ u16 etnaviv_buffer_init(struct etnaviv_gpu *gpu) 
	buffer->user_size = 0;



	CMD_WAIT(buffer);

	CMD_LINK(buffer, 2, etnaviv_cmdbuf_get_va(buffer) +

		 buffer->user_size - 4);

	CMD_LINK(buffer, 2,

		 etnaviv_cmdbuf_get_va(buffer, &gpu->mmu_context->cmdbuf_mapping)

		 + buffer->user_size - 4);



	return buffer->user_size / 8;

}
@@ -203,7 +210,7 @@ u16 etnaviv_buffer_config_mmuv2(struct etnaviv_gpu *gpu, u32 mtlb_addr, u32 safe 
	return buffer->user_size / 8;

}



u16 etnaviv_buffer_config_pta(struct etnaviv_gpu *gpu)

u16 etnaviv_buffer_config_pta(struct etnaviv_gpu *gpu, unsigned short id)

{

	struct etnaviv_cmdbuf *buffer = &gpu->buffer;
@@ -212,7 +219,7 @@ u16 etnaviv_buffer_config_pta(struct etnaviv_gpu *gpu) 
	buffer->user_size = 0;



	CMD_LOAD_STATE(buffer, VIVS_MMUv2_PTA_CONFIG,

		       VIVS_MMUv2_PTA_CONFIG_INDEX(0));

		       VIVS_MMUv2_PTA_CONFIG_INDEX(id));



	CMD_END(buffer);
@@ -289,8 +296,9 @@ void etnaviv_sync_point_queue(struct etnaviv_gpu *gpu, unsigned int event) 


	/* Append waitlink */

	CMD_WAIT(buffer);

	CMD_LINK(buffer, 2, etnaviv_cmdbuf_get_va(buffer) +

			    buffer->user_size - 4);

	CMD_LINK(buffer, 2,

		 etnaviv_cmdbuf_get_va(buffer, &gpu->mmu_context->cmdbuf_mapping)

		 + buffer->user_size - 4);



	/*

	 * Kick off the 'sync point' command by replacing the previous
@@ -304,36 +312,41 @@ void etnaviv_sync_point_queue(struct etnaviv_gpu *gpu, unsigned int event) 


/* Append a command buffer to the ring buffer. */

void etnaviv_buffer_queue(struct etnaviv_gpu *gpu, u32 exec_state,

	unsigned int event, struct etnaviv_cmdbuf *cmdbuf)

	struct etnaviv_iommu_context *mmu_context, unsigned int event,

	struct etnaviv_cmdbuf *cmdbuf)

{

	struct etnaviv_cmdbuf *buffer = &gpu->buffer;

	unsigned int waitlink_offset = buffer->user_size - 16;

	u32 return_target, return_dwords;

	u32 link_target, link_dwords;

	bool switch_context = gpu->exec_state != exec_state;

	bool switch_mmu_context = gpu->mmu_context != mmu_context;

	unsigned int new_flush_seq = READ_ONCE(gpu->mmu_context->flush_seq);

	bool need_flush = switch_mmu_context || gpu->flush_seq != new_flush_seq;



	lockdep_assert_held(&gpu->lock);



	if (drm_debug & DRM_UT_DRIVER)

		etnaviv_buffer_dump(gpu, buffer, 0, 0x50);



	link_target = etnaviv_cmdbuf_get_va(cmdbuf);

	link_target = etnaviv_cmdbuf_get_va(cmdbuf,

					    &gpu->mmu_context->cmdbuf_mapping);

	link_dwords = cmdbuf->size / 8;



	/*

	 * If we need maintanence prior to submitting this buffer, we will

	 * If we need maintenance prior to submitting this buffer, we will

	 * need to append a mmu flush load state, followed by a new

	 * link to this buffer - a total of four additional words.

	 */

	if (gpu->mmu->need_flush || switch_context) {

	if (need_flush || switch_context) {

		u32 target, extra_dwords;



		/* link command */

		extra_dwords = 1;



		/* flush command */

		if (gpu->mmu->need_flush) {

			if (gpu->mmu->version == ETNAVIV_IOMMU_V1)

		if (need_flush) {

			if (gpu->mmu_context->global->version == ETNAVIV_IOMMU_V1)

				extra_dwords += 1;

			else

				extra_dwords += 3;
@@ -343,11 +356,28 @@ void etnaviv_buffer_queue(struct etnaviv_gpu *gpu, u32 exec_state, 
		if (switch_context)

			extra_dwords += 4;



		/* PTA load command */

		if (switch_mmu_context && gpu->sec_mode == ETNA_SEC_KERNEL)

			extra_dwords += 1;



		target = etnaviv_buffer_reserve(gpu, buffer, extra_dwords);

		/*

		 * Switch MMU context if necessary. Must be done after the

		 * link target has been calculated, as the jump forward in the

		 * kernel ring still uses the last active MMU context before

		 * the switch.

		 */

		if (switch_mmu_context) {

			struct etnaviv_iommu_context *old_context = gpu->mmu_context;



		if (gpu->mmu->need_flush) {

			etnaviv_iommu_context_get(mmu_context);

			gpu->mmu_context = mmu_context;

			etnaviv_iommu_context_put(old_context);

		}



		if (need_flush) {

			/* Add the MMU flush */

			if (gpu->mmu->version == ETNAVIV_IOMMU_V1) {

			if (gpu->mmu_context->global->version == ETNAVIV_IOMMU_V1) {

				CMD_LOAD_STATE(buffer, VIVS_GL_FLUSH_MMU,

					       VIVS_GL_FLUSH_MMU_FLUSH_FEMMU |

					       VIVS_GL_FLUSH_MMU_FLUSH_UNK1 |
@@ -355,17 +385,30 @@ void etnaviv_buffer_queue(struct etnaviv_gpu *gpu, u32 exec_state, 
					       VIVS_GL_FLUSH_MMU_FLUSH_PEMMU |

					       VIVS_GL_FLUSH_MMU_FLUSH_UNK4);

			} else {

				u32 flush = VIVS_MMUv2_CONFIGURATION_MODE_MASK |

					    VIVS_MMUv2_CONFIGURATION_FLUSH_FLUSH;



				if (switch_mmu_context &&

				    gpu->sec_mode == ETNA_SEC_KERNEL) {

					unsigned short id =

						etnaviv_iommuv2_get_pta_id(gpu->mmu_context);

					CMD_LOAD_STATE(buffer,

						VIVS_MMUv2_PTA_CONFIG,

						VIVS_MMUv2_PTA_CONFIG_INDEX(id));

				}



				if (gpu->sec_mode == ETNA_SEC_NONE)

					flush |= etnaviv_iommuv2_get_mtlb_addr(gpu->mmu_context);



				CMD_LOAD_STATE(buffer, VIVS_MMUv2_CONFIGURATION,

					VIVS_MMUv2_CONFIGURATION_MODE_MASK |

					VIVS_MMUv2_CONFIGURATION_ADDRESS_MASK |

					VIVS_MMUv2_CONFIGURATION_FLUSH_FLUSH);

					       flush);

				CMD_SEM(buffer, SYNC_RECIPIENT_FE,

					SYNC_RECIPIENT_PE);

				CMD_STALL(buffer, SYNC_RECIPIENT_FE,

					SYNC_RECIPIENT_PE);

			}



			gpu->mmu->need_flush = false;

			gpu->flush_seq = new_flush_seq;

		}



		if (switch_context) {
@@ -374,6 +417,8 @@ void etnaviv_buffer_queue(struct etnaviv_gpu *gpu, u32 exec_state, 
		}



		/* And the link to the submitted buffer */

		link_target = etnaviv_cmdbuf_get_va(cmdbuf,

					&gpu->mmu_context->cmdbuf_mapping);

		CMD_LINK(buffer, link_dwords, link_target);



		/* Update the link target to point to above instructions */
@@ -410,12 +455,14 @@ void etnaviv_buffer_queue(struct etnaviv_gpu *gpu, u32 exec_state, 
	CMD_LOAD_STATE(buffer, VIVS_GL_EVENT, VIVS_GL_EVENT_EVENT_ID(event) |

		       VIVS_GL_EVENT_FROM_PE);

	CMD_WAIT(buffer);

	CMD_LINK(buffer, 2, etnaviv_cmdbuf_get_va(buffer) +

			    buffer->user_size - 4);

	CMD_LINK(buffer, 2,

		 etnaviv_cmdbuf_get_va(buffer, &gpu->mmu_context->cmdbuf_mapping)

		 + buffer->user_size - 4);



	if (drm_debug & DRM_UT_DRIVER)

		pr_info("stream link to 0x%08x @ 0x%08x %p\n",

			return_target, etnaviv_cmdbuf_get_va(cmdbuf),

			return_target,

			etnaviv_cmdbuf_get_va(cmdbuf, &gpu->mmu_context->cmdbuf_mapping),

			cmdbuf->vaddr);



	if (drm_debug & DRM_UT_DRIVER) {

drivers/gpu/drm/etnaviv/etnaviv_cmdbuf.c

+33 −25
Original line number Diff line number Diff line
@@ -3,27 +3,26 @@ 
 * Copyright (C) 2017-2018 Etnaviv Project

 */



#include <linux/dma-mapping.h>



#include <drm/drm_mm.h>



#include "etnaviv_cmdbuf.h"

#include "etnaviv_gem.h"

#include "etnaviv_gpu.h"

#include "etnaviv_mmu.h"

#include "etnaviv_perfmon.h"



#define SUBALLOC_SIZE		SZ_256K

#define SUBALLOC_SIZE		SZ_512K

#define SUBALLOC_GRANULE	SZ_4K

#define SUBALLOC_GRANULES	(SUBALLOC_SIZE / SUBALLOC_GRANULE)



struct etnaviv_cmdbuf_suballoc {

	/* suballocated dma buffer properties */

	struct etnaviv_gpu *gpu;

	struct device *dev;

	void *vaddr;

	dma_addr_t paddr;



	/* GPU mapping */

	u32 iova;

	struct drm_mm_node vram_node; /* only used on MMUv2 */



	/* allocation management */

	struct mutex lock;

	DECLARE_BITMAP(granule_map, SUBALLOC_GRANULES);
@@ -32,7 +31,7 @@ struct etnaviv_cmdbuf_suballoc { 
};



struct etnaviv_cmdbuf_suballoc *

etnaviv_cmdbuf_suballoc_new(struct etnaviv_gpu * gpu)

etnaviv_cmdbuf_suballoc_new(struct device *dev)

{

	struct etnaviv_cmdbuf_suballoc *suballoc;

	int ret;
@@ -41,36 +40,44 @@ etnaviv_cmdbuf_suballoc_new(struct etnaviv_gpu * gpu) 
	if (!suballoc)

		return ERR_PTR(-ENOMEM);



	suballoc->gpu = gpu;

	suballoc->dev = dev;

	mutex_init(&suballoc->lock);

	init_waitqueue_head(&suballoc->free_event);



	suballoc->vaddr = dma_alloc_wc(gpu->dev, SUBALLOC_SIZE,

	BUILD_BUG_ON(ETNAVIV_SOFTPIN_START_ADDRESS < SUBALLOC_SIZE);

	suballoc->vaddr = dma_alloc_wc(dev, SUBALLOC_SIZE,

				       &suballoc->paddr, GFP_KERNEL);

	if (!suballoc->vaddr)

	if (!suballoc->vaddr) {

		ret = -ENOMEM;

		goto free_suballoc;



	ret = etnaviv_iommu_get_suballoc_va(gpu, suballoc->paddr,

					    &suballoc->vram_node, SUBALLOC_SIZE,

					    &suballoc->iova);

	if (ret)

		goto free_dma;

	}



	return suballoc;



free_dma:

	dma_free_wc(gpu->dev, SUBALLOC_SIZE, suballoc->vaddr, suballoc->paddr);

free_suballoc:

	kfree(suballoc);



	return NULL;

	return ERR_PTR(ret);

}



int etnaviv_cmdbuf_suballoc_map(struct etnaviv_cmdbuf_suballoc *suballoc,

				struct etnaviv_iommu_context *context,

				struct etnaviv_vram_mapping *mapping,

				u32 memory_base)

{

	return etnaviv_iommu_get_suballoc_va(context, mapping, memory_base,

					     suballoc->paddr, SUBALLOC_SIZE);

}



void etnaviv_cmdbuf_suballoc_unmap(struct etnaviv_iommu_context *context,

				   struct etnaviv_vram_mapping *mapping)

{

	etnaviv_iommu_put_suballoc_va(context, mapping);

}



void etnaviv_cmdbuf_suballoc_destroy(struct etnaviv_cmdbuf_suballoc *suballoc)

{

	etnaviv_iommu_put_suballoc_va(suballoc->gpu, &suballoc->vram_node,

				      SUBALLOC_SIZE, suballoc->iova);

	dma_free_wc(suballoc->gpu->dev, SUBALLOC_SIZE, suballoc->vaddr,

	dma_free_wc(suballoc->dev, SUBALLOC_SIZE, suballoc->vaddr,

		    suballoc->paddr);

	kfree(suballoc);

}
@@ -95,7 +102,7 @@ retry: 
						       suballoc->free_space,

						       msecs_to_jiffies(10 * 1000));

		if (!ret) {

			dev_err(suballoc->gpu->dev,

			dev_err(suballoc->dev,

				"Timeout waiting for cmdbuf space\n");

			return -ETIMEDOUT;

		}
@@ -123,9 +130,10 @@ void etnaviv_cmdbuf_free(struct etnaviv_cmdbuf *cmdbuf) 
	wake_up_all(&suballoc->free_event);

}



u32 etnaviv_cmdbuf_get_va(struct etnaviv_cmdbuf *buf)

u32 etnaviv_cmdbuf_get_va(struct etnaviv_cmdbuf *buf,

			  struct etnaviv_vram_mapping *mapping)

{

	return buf->suballoc->iova + buf->suballoc_offset;

	return mapping->iova + buf->suballoc_offset;

}



dma_addr_t etnaviv_cmdbuf_get_pa(struct etnaviv_cmdbuf *buf)

drivers/gpu/drm/etnaviv/etnaviv_cmdbuf.h

+12 −3
Original line number Diff line number Diff line
@@ -8,7 +8,9 @@ 


#include <linux/types.h>



struct etnaviv_gpu;

struct device;

struct etnaviv_iommu_context;

struct etnaviv_vram_mapping;

struct etnaviv_cmdbuf_suballoc;

struct etnaviv_perfmon_request;
@@ -23,15 +25,22 @@ struct etnaviv_cmdbuf { 
};



struct etnaviv_cmdbuf_suballoc *

etnaviv_cmdbuf_suballoc_new(struct etnaviv_gpu * gpu);

etnaviv_cmdbuf_suballoc_new(struct device *dev);

void etnaviv_cmdbuf_suballoc_destroy(struct etnaviv_cmdbuf_suballoc *suballoc);

int etnaviv_cmdbuf_suballoc_map(struct etnaviv_cmdbuf_suballoc *suballoc,

				struct etnaviv_iommu_context *context,

				struct etnaviv_vram_mapping *mapping,

				u32 memory_base);

void etnaviv_cmdbuf_suballoc_unmap(struct etnaviv_iommu_context *context,

				   struct etnaviv_vram_mapping *mapping);





int etnaviv_cmdbuf_init(struct etnaviv_cmdbuf_suballoc *suballoc,

		struct etnaviv_cmdbuf *cmdbuf, u32 size);

void etnaviv_cmdbuf_free(struct etnaviv_cmdbuf *cmdbuf);



u32 etnaviv_cmdbuf_get_va(struct etnaviv_cmdbuf *buf);

u32 etnaviv_cmdbuf_get_va(struct etnaviv_cmdbuf *buf,

			  struct etnaviv_vram_mapping *mapping);

dma_addr_t etnaviv_cmdbuf_get_pa(struct etnaviv_cmdbuf *buf);



#endif /* __ETNAVIV_CMDBUF_H__ */

drivers/gpu/drm/etnaviv/etnaviv_drv.c

+59 −9
Original line number Diff line number Diff line
@@ -4,8 +4,17 @@ 
 */



#include <linux/component.h>

#include <linux/dma-mapping.h>

#include <linux/module.h>

#include <linux/of_platform.h>

#include <linux/uaccess.h>



#include <drm/drm_debugfs.h>

#include <drm/drm_drv.h>

#include <drm/drm_file.h>

#include <drm/drm_ioctl.h>

#include <drm/drm_of.h>

#include <drm/drm_prime.h>



#include "etnaviv_cmdbuf.h"

#include "etnaviv_drv.h"
@@ -41,12 +50,19 @@ static int etnaviv_open(struct drm_device *dev, struct drm_file *file) 
{

	struct etnaviv_drm_private *priv = dev->dev_private;

	struct etnaviv_file_private *ctx;

	int i;

	int ret, i;



	ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);

	if (!ctx)

		return -ENOMEM;



	ctx->mmu = etnaviv_iommu_context_init(priv->mmu_global,

					      priv->cmdbuf_suballoc);

	if (!ctx->mmu) {

		ret = -ENOMEM;

		goto out_free;

	}



	for (i = 0; i < ETNA_MAX_PIPES; i++) {

		struct etnaviv_gpu *gpu = priv->gpu[i];

		struct drm_sched_rq *rq;
@@ -61,6 +77,10 @@ static int etnaviv_open(struct drm_device *dev, struct drm_file *file) 
	file->driver_priv = ctx;



	return 0;



out_free:

	kfree(ctx);

	return ret;

}



static void etnaviv_postclose(struct drm_device *dev, struct drm_file *file)
@@ -76,6 +96,8 @@ static void etnaviv_postclose(struct drm_device *dev, struct drm_file *file) 
			drm_sched_entity_destroy(&ctx->sched_entity[i]);

	}



	etnaviv_iommu_context_put(ctx->mmu);



	kfree(ctx);

}
@@ -107,12 +129,29 @@ static int etnaviv_mm_show(struct drm_device *dev, struct seq_file *m) 
static int etnaviv_mmu_show(struct etnaviv_gpu *gpu, struct seq_file *m)

{

	struct drm_printer p = drm_seq_file_printer(m);

	struct etnaviv_iommu_context *mmu_context;



	seq_printf(m, "Active Objects (%s):\n", dev_name(gpu->dev));



	mutex_lock(&gpu->mmu->lock);

	drm_mm_print(&gpu->mmu->mm, &p);

	mutex_unlock(&gpu->mmu->lock);

	/*

	 * Lock the GPU to avoid a MMU context switch just now and elevate

	 * the refcount of the current context to avoid it disappearing from

	 * under our feet.

	 */

	mutex_lock(&gpu->lock);

	mmu_context = gpu->mmu_context;

	if (mmu_context)

		etnaviv_iommu_context_get(mmu_context);

	mutex_unlock(&gpu->lock);



	if (!mmu_context)

		return 0;



	mutex_lock(&mmu_context->lock);

	drm_mm_print(&mmu_context->mm, &p);

	mutex_unlock(&mmu_context->lock);



	etnaviv_iommu_context_put(mmu_context);



	return 0;

}
@@ -486,7 +525,7 @@ static struct drm_driver etnaviv_drm_driver = { 
	.desc               = "etnaviv DRM",

	.date               = "20151214",

	.major              = 1,

	.minor              = 2,

	.minor              = 3,

};



/*
@@ -517,23 +556,32 @@ static int etnaviv_bind(struct device *dev) 
	INIT_LIST_HEAD(&priv->gem_list);

	priv->num_gpus = 0;



	priv->cmdbuf_suballoc = etnaviv_cmdbuf_suballoc_new(drm->dev);

	if (IS_ERR(priv->cmdbuf_suballoc)) {

		dev_err(drm->dev, "Failed to create cmdbuf suballocator\n");

		ret = PTR_ERR(priv->cmdbuf_suballoc);

		goto out_free_priv;

	}



	dev_set_drvdata(dev, drm);



	ret = component_bind_all(dev, drm);

	if (ret < 0)

		goto out_bind;

		goto out_destroy_suballoc;



	load_gpu(drm);



	ret = drm_dev_register(drm, 0);

	if (ret)

		goto out_register;

		goto out_unbind;



	return 0;



out_register:

out_unbind:

	component_unbind_all(dev, drm);

out_bind:

out_destroy_suballoc:

	etnaviv_cmdbuf_suballoc_destroy(priv->cmdbuf_suballoc);

out_free_priv:

	kfree(priv);

out_put:

	drm_dev_put(drm);
@@ -552,6 +600,8 @@ static void etnaviv_unbind(struct device *dev) 


	dev->dma_parms = NULL;



	etnaviv_cmdbuf_suballoc_destroy(priv->cmdbuf_suballoc);



	drm->dev_private = NULL;

	kfree(priv);

drivers/gpu/drm/etnaviv/etnaviv_drv.h

+11 −16
Original line number Diff line number Diff line
@@ -6,21 +6,12 @@ 
#ifndef __ETNAVIV_DRV_H__

#define __ETNAVIV_DRV_H__



#include <linux/kernel.h>

#include <linux/clk.h>

#include <linux/cpufreq.h>

#include <linux/module.h>

#include <linux/platform_device.h>

#include <linux/pm.h>

#include <linux/pm_runtime.h>

#include <linux/slab.h>

#include <linux/list.h>

#include <linux/mm_types.h>

#include <linux/sizes.h>

#include <linux/time64.h>

#include <linux/types.h>

#include <linux/sizes.h>

#include <linux/mm_types.h>



#include <drm/drmP.h>

#include <drm/drm_fb_helper.h>

#include <drm/drm_gem.h>

#include <drm/etnaviv_drm.h>
@@ -31,12 +22,12 @@ struct etnaviv_gpu; 
struct etnaviv_mmu;

struct etnaviv_gem_object;

struct etnaviv_gem_submit;

struct etnaviv_iommu_global;



#define ETNAVIV_SOFTPIN_START_ADDRESS	SZ_4M /* must be >= SUBALLOC_SIZE */



struct etnaviv_file_private {

	/*

	 * When per-context address spaces are supported we'd keep track of

	 * the context's page-tables here.

	 */

	struct etnaviv_iommu_context	*mmu;

	struct drm_sched_entity		sched_entity[ETNA_MAX_PIPES];

};
@@ -45,6 +36,9 @@ struct etnaviv_drm_private { 
	struct device_dma_parameters dma_parms;

	struct etnaviv_gpu *gpu[ETNA_MAX_PIPES];



	struct etnaviv_cmdbuf_suballoc *cmdbuf_suballoc;

	struct etnaviv_iommu_global *mmu_global;



	/* list of GEM objects: */

	struct mutex gem_lock;

	struct list_head gem_list;
@@ -76,10 +70,11 @@ int etnaviv_gem_new_userptr(struct drm_device *dev, struct drm_file *file, 
	uintptr_t ptr, u32 size, u32 flags, u32 *handle);

u16 etnaviv_buffer_init(struct etnaviv_gpu *gpu);

u16 etnaviv_buffer_config_mmuv2(struct etnaviv_gpu *gpu, u32 mtlb_addr, u32 safe_addr);

u16 etnaviv_buffer_config_pta(struct etnaviv_gpu *gpu);

u16 etnaviv_buffer_config_pta(struct etnaviv_gpu *gpu, unsigned short id);

void etnaviv_buffer_end(struct etnaviv_gpu *gpu);

void etnaviv_sync_point_queue(struct etnaviv_gpu *gpu, unsigned int event);

void etnaviv_buffer_queue(struct etnaviv_gpu *gpu, u32 exec_state,

	struct etnaviv_iommu_context *mmu,

	unsigned int event, struct etnaviv_cmdbuf *cmdbuf);

void etnaviv_validate_init(void);

bool etnaviv_cmd_validate_one(struct etnaviv_gpu *gpu,

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