dt-bindings: add register based devices' mux controller DT bindings

MMIO register bitfield-based multiplexer controller bindings

Define register bitfields to be used to control multiplexers. The parent

device tree node must be a syscon node to provide register access.

Required properties:

- compatible : "mmio-mux"

- #mux-control-cells : <1>

- mux-reg-masks : an array of register offset and pre-shifted bitfield mask

                  pairs, each describing a single mux control.

* Standard mux-controller bindings as decribed in mux-controller.txt

Optional properties:

- idle-states : if present, the state the muxes will have when idle. The

		special state MUX_IDLE_AS_IS is the default.

The multiplexer state of each multiplexer is defined as the value of the

bitfield described by the corresponding register offset and bitfield mask pair

in the mux-reg-masks array, accessed through the parent syscon.

Example:

	syscon {

		compatible = "syscon";

		mux: mux-controller {

			compatible = "mmio-mux";

			#mux-control-cells = <1>;

			mux-reg-masks = <0x3 0x30>, /* 0: reg 0x3, bits 5:4 */

					<0x3 0x40>, /* 1: reg 0x3, bit 6 */

			idle-states = <MUX_IDLE_AS_IS>, <0>;

		};

	};

	video-mux {

		compatible = "video-mux";

		mux-controls = <&mux 0>;

		ports {

			/* inputs 0..3 */

			port@0 {

				reg = <0>;

			};

			port@1 {

				reg = <1>;

			};

			port@2 {

				reg = <2>;

			};

			port@3 {

				reg = <3>;

			};

			/* output */

			port@4 {

				reg = <4>;

			};

		};

	};

Generic register bitfield-based multiplexer controller bindings

Define register bitfields to be used to control multiplexers. The parent

device tree node must be a device node to provide register r/w access.

Required properties:

- compatible : should be one of

	"reg-mux" : if parent device of mux controller is not syscon device

	"mmio-mux" : if parent device of mux controller is syscon device

- #mux-control-cells : <1>

- mux-reg-masks : an array of register offset and pre-shifted bitfield mask

                  pairs, each describing a single mux control.

* Standard mux-controller bindings as decribed in mux-controller.txt

Optional properties:

- idle-states : if present, the state the muxes will have when idle. The

		special state MUX_IDLE_AS_IS is the default.

The multiplexer state of each multiplexer is defined as the value of the

bitfield described by the corresponding register offset and bitfield mask

pair in the mux-reg-masks array.

Example 1:

The parent device of mux controller is not a syscon device.

&i2c0 {

	fpga@66 { // fpga connected to i2c

		compatible = "fsl,lx2160aqds-fpga", "fsl,fpga-qixis-i2c",

			     "simple-mfd";

		reg = <0x66>;

		mux: mux-controller {

			compatible = "reg-mux";

			#mux-control-cells = <1>;

			mux-reg-masks = <0x54 0xf8>, /* 0: reg 0x54, bits 7:3 */

					<0x54 0x07>; /* 1: reg 0x54, bits 2:0 */

		};

	};

};

mdio-mux-1 {

	compatible = "mdio-mux-multiplexer";

	mux-controls = <&mux 0>;

	mdio-parent-bus = <&emdio1>;

	#address-cells = <1>;

	#size-cells = <0>;

	mdio@0 {

		reg = <0x0>;

		#address-cells = <1>;

		#size-cells = <0>;

	};

	mdio@8 {

		reg = <0x8>;

		#address-cells = <1>;

		#size-cells = <0>;

	};

	..

	..

};

mdio-mux-2 {

	compatible = "mdio-mux-multiplexer";

	mux-controls = <&mux 1>;

	mdio-parent-bus = <&emdio2>;

	#address-cells = <1>;

	#size-cells = <0>;

	mdio@0 {

		reg = <0x0>;

		#address-cells = <1>;

		#size-cells = <0>;

	};

	mdio@1 {

		reg = <0x1>;

		#address-cells = <1>;

		#size-cells = <0>;

	};

	..

	..

};

Example 2:

The parent device of mux controller is syscon device.

syscon {

	compatible = "syscon";

	mux: mux-controller {

		compatible = "mmio-mux";

		#mux-control-cells = <1>;

		mux-reg-masks = <0x3 0x30>, /* 0: reg 0x3, bits 5:4 */

				<0x3 0x40>, /* 1: reg 0x3, bit 6 */

		idle-states = <MUX_IDLE_AS_IS>, <0>;

	};

};

video-mux {

	compatible = "video-mux";

	mux-controls = <&mux 0>;

	#address-cells = <1>;

	#size-cells = <0>;

	ports {

		/* inputs 0..3 */

		port@0 {

			reg = <0>;

		};

		port@1 {

			reg = <1>;

		};

		port@2 {

			reg = <2>;

		};

		port@3 {

			reg = <3>;

		};

		/* output */

		port@4 {

			reg = <4>;

		};

	};

};