Commit ae0645a4 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge branch 'for-linus' of git://git.o-hand.com/linux-mfd 

* 'for-linus' of git://git.o-hand.com/linux-mfd:
  mfd: let asic3 use mem resource instead of bus_shift
  mfd: remove DS1WM register definitions from asic3.h
  mfd: add ASIC3_CONFIG_GPIO templates
  mfd: fix the asic3 irq demux code
  mfd: asic3 should depend on gpiolib
  mfd: fix asic3 config array initialisation
  mfd: move asic3 probe functions into __init section
  mfd: Use uppercase only for asic3 macros and defines
  mfd: use dev_* macros for asic3 debugging
  mfd: New asic3 gpio configuration code
  mfd: asic3 children platform data removal
  mfd: asic3 gpiolib support
parents f894d183 99cdb0c8

drivers/mfd/Kconfig

+1 −1
Original line number Diff line number Diff line
@@ -17,7 +17,7 @@ config MFD_SM501 


config MFD_ASIC3

	bool "Support for Compaq ASIC3"

	depends on GENERIC_HARDIRQS && ARM

	depends on GENERIC_HARDIRQS && HAVE_GPIO_LIB && ARM

	 ---help---

	  This driver supports the ASIC3 multifunction chip found on many

	  PDAs (mainly iPAQ and HTC based ones)

drivers/mfd/asic3.c

+223 −165
Original line number Diff line number Diff line
@@ -9,7 +9,7 @@ 
 *

 * Copyright 2001 Compaq Computer Corporation.

 * Copyright 2004-2005 Phil Blundell

 * Copyright 2007 OpenedHand Ltd.

 * Copyright 2007-2008 OpenedHand Ltd.

 *

 * Authors: Phil Blundell <pb@handhelds.org>,

 *	    Samuel Ortiz <sameo@openedhand.com>
@@ -19,12 +19,26 @@ 
#include <linux/version.h>

#include <linux/kernel.h>

#include <linux/irq.h>

#include <linux/gpio.h>

#include <linux/io.h>

#include <linux/spinlock.h>

#include <linux/platform_device.h>



#include <linux/mfd/asic3.h>



struct asic3 {

	void __iomem *mapping;

	unsigned int bus_shift;

	unsigned int irq_nr;

	unsigned int irq_base;

	spinlock_t lock;

	u16 irq_bothedge[4];

	struct gpio_chip gpio;

	struct device *dev;

};



static int asic3_gpio_get(struct gpio_chip *chip, unsigned offset);



static inline void asic3_write_register(struct asic3 *asic,

				 unsigned int reg, u32 value)

{
@@ -41,8 +55,8 @@ static inline u32 asic3_read_register(struct asic3 *asic, 


/* IRQs */

#define MAX_ASIC_ISR_LOOPS    20

#define ASIC3_GPIO_Base_INCR \

	(ASIC3_GPIO_B_Base - ASIC3_GPIO_A_Base)

#define ASIC3_GPIO_BASE_INCR \

	(ASIC3_GPIO_B_BASE - ASIC3_GPIO_A_BASE)



static void asic3_irq_flip_edge(struct asic3 *asic,

				u32 base, int bit)
@@ -52,10 +66,10 @@ static void asic3_irq_flip_edge(struct asic3 *asic, 


	spin_lock_irqsave(&asic->lock, flags);

	edge = asic3_read_register(asic,

				   base + ASIC3_GPIO_EdgeTrigger);

				   base + ASIC3_GPIO_EDGE_TRIGGER);

	edge ^= bit;

	asic3_write_register(asic,

			     base + ASIC3_GPIO_EdgeTrigger, edge);

			     base + ASIC3_GPIO_EDGE_TRIGGER, edge);

	spin_unlock_irqrestore(&asic->lock, flags);

}
@@ -75,7 +89,7 @@ static void asic3_irq_demux(unsigned int irq, struct irq_desc *desc) 


		spin_lock_irqsave(&asic->lock, flags);

		status = asic3_read_register(asic,

					     ASIC3_OFFSET(INTR, PIntStat));

					     ASIC3_OFFSET(INTR, P_INT_STAT));

		spin_unlock_irqrestore(&asic->lock, flags);



		/* Check all ten register bits */
@@ -87,17 +101,17 @@ static void asic3_irq_demux(unsigned int irq, struct irq_desc *desc) 
			if (status & (1 << bank)) {

				unsigned long base, istat;



				base = ASIC3_GPIO_A_Base

				       + bank * ASIC3_GPIO_Base_INCR;

				base = ASIC3_GPIO_A_BASE

				       + bank * ASIC3_GPIO_BASE_INCR;



				spin_lock_irqsave(&asic->lock, flags);

				istat = asic3_read_register(asic,

							    base +

							    ASIC3_GPIO_IntStatus);

							    ASIC3_GPIO_INT_STATUS);

				/* Clearing IntStatus */

				asic3_write_register(asic,

						     base +

						     ASIC3_GPIO_IntStatus, 0);

						     ASIC3_GPIO_INT_STATUS, 0);

				spin_unlock_irqrestore(&asic->lock, flags);



				for (i = 0; i < ASIC3_GPIOS_PER_BANK; i++) {
@@ -123,7 +137,7 @@ static void asic3_irq_demux(unsigned int irq, struct irq_desc *desc) 
		for (i = ASIC3_NUM_GPIOS; i < ASIC3_NR_IRQS; i++) {

			/* They start at bit 4 and go up */

			if (status & (1 << (i - ASIC3_NUM_GPIOS + 4))) {

				desc = irq_desc +  + i;

				desc = irq_desc + asic->irq_base + i;

				desc->handle_irq(asic->irq_base + i,

						 desc);

			}
@@ -131,8 +145,7 @@ static void asic3_irq_demux(unsigned int irq, struct irq_desc *desc) 
	}



	if (iter >= MAX_ASIC_ISR_LOOPS)

		printk(KERN_ERR "%s: interrupt processing overrun\n",

		       __func__);

		dev_err(asic->dev, "interrupt processing overrun\n");

}



static inline int asic3_irq_to_bank(struct asic3 *asic, int irq)
@@ -141,7 +154,7 @@ static inline int asic3_irq_to_bank(struct asic3 *asic, int irq) 


	n = (irq - asic->irq_base) >> 4;



	return (n * (ASIC3_GPIO_B_Base - ASIC3_GPIO_A_Base));

	return (n * (ASIC3_GPIO_B_BASE - ASIC3_GPIO_A_BASE));

}



static inline int asic3_irq_to_index(struct asic3 *asic, int irq)
@@ -159,9 +172,9 @@ static void asic3_mask_gpio_irq(unsigned int irq) 
	index = asic3_irq_to_index(asic, irq);



	spin_lock_irqsave(&asic->lock, flags);

	val = asic3_read_register(asic, bank + ASIC3_GPIO_Mask);

	val = asic3_read_register(asic, bank + ASIC3_GPIO_MASK);

	val |= 1 << index;

	asic3_write_register(asic, bank + ASIC3_GPIO_Mask, val);

	asic3_write_register(asic, bank + ASIC3_GPIO_MASK, val);

	spin_unlock_irqrestore(&asic->lock, flags);

}
@@ -173,15 +186,15 @@ static void asic3_mask_irq(unsigned int irq) 


	spin_lock_irqsave(&asic->lock, flags);

	regval = asic3_read_register(asic,

				     ASIC3_INTR_Base +

				     ASIC3_INTR_IntMask);

				     ASIC3_INTR_BASE +

				     ASIC3_INTR_INT_MASK);



	regval &= ~(ASIC3_INTMASK_MASK0 <<

		    (irq - (asic->irq_base + ASIC3_NUM_GPIOS)));



	asic3_write_register(asic,

			     ASIC3_INTR_Base +

			     ASIC3_INTR_IntMask,

			     ASIC3_INTR_BASE +

			     ASIC3_INTR_INT_MASK,

			     regval);

	spin_unlock_irqrestore(&asic->lock, flags);

}
@@ -196,9 +209,9 @@ static void asic3_unmask_gpio_irq(unsigned int irq) 
	index = asic3_irq_to_index(asic, irq);



	spin_lock_irqsave(&asic->lock, flags);

	val = asic3_read_register(asic, bank + ASIC3_GPIO_Mask);

	val = asic3_read_register(asic, bank + ASIC3_GPIO_MASK);

	val &= ~(1 << index);

	asic3_write_register(asic, bank + ASIC3_GPIO_Mask, val);

	asic3_write_register(asic, bank + ASIC3_GPIO_MASK, val);

	spin_unlock_irqrestore(&asic->lock, flags);

}
@@ -210,15 +223,15 @@ static void asic3_unmask_irq(unsigned int irq) 


	spin_lock_irqsave(&asic->lock, flags);

	regval = asic3_read_register(asic,

				     ASIC3_INTR_Base +

				     ASIC3_INTR_IntMask);

				     ASIC3_INTR_BASE +

				     ASIC3_INTR_INT_MASK);



	regval |= (ASIC3_INTMASK_MASK0 <<

		   (irq - (asic->irq_base + ASIC3_NUM_GPIOS)));



	asic3_write_register(asic,

			     ASIC3_INTR_Base +

			     ASIC3_INTR_IntMask,

			     ASIC3_INTR_BASE +

			     ASIC3_INTR_INT_MASK,

			     regval);

	spin_unlock_irqrestore(&asic->lock, flags);

}
@@ -236,11 +249,11 @@ static int asic3_gpio_irq_type(unsigned int irq, unsigned int type) 


	spin_lock_irqsave(&asic->lock, flags);

	level = asic3_read_register(asic,

				    bank + ASIC3_GPIO_LevelTrigger);

				    bank + ASIC3_GPIO_LEVEL_TRIGGER);

	edge = asic3_read_register(asic,

				   bank + ASIC3_GPIO_EdgeTrigger);

				   bank + ASIC3_GPIO_EDGE_TRIGGER);

	trigger = asic3_read_register(asic,

				      bank + ASIC3_GPIO_TriggerType);

				      bank + ASIC3_GPIO_TRIGGER_TYPE);

	asic->irq_bothedge[(irq - asic->irq_base) >> 4] &= ~bit;



	if (type == IRQT_RISING) {
@@ -251,7 +264,7 @@ static int asic3_gpio_irq_type(unsigned int irq, unsigned int type) 
		edge &= ~bit;

	} else if (type == IRQT_BOTHEDGE) {

		trigger |= bit;

		if (asic3_gpio_get_value(asic, irq - asic->irq_base))

		if (asic3_gpio_get(&asic->gpio, irq - asic->irq_base))

			edge &= ~bit;

		else

			edge |= bit;
@@ -268,13 +281,13 @@ static int asic3_gpio_irq_type(unsigned int irq, unsigned int type) 
		 * be careful to not unmask them if mask was also called.

		 * Probably need internal state for mask.

		 */

		printk(KERN_NOTICE "asic3: irq type not changed.\n");

		dev_notice(asic->dev, "irq type not changed\n");

	}

	asic3_write_register(asic, bank + ASIC3_GPIO_LevelTrigger,

	asic3_write_register(asic, bank + ASIC3_GPIO_LEVEL_TRIGGER,

			     level);

	asic3_write_register(asic, bank + ASIC3_GPIO_EdgeTrigger,

	asic3_write_register(asic, bank + ASIC3_GPIO_EDGE_TRIGGER,

			     edge);

	asic3_write_register(asic, bank + ASIC3_GPIO_TriggerType,

	asic3_write_register(asic, bank + ASIC3_GPIO_TRIGGER_TYPE,

			     trigger);

	spin_unlock_irqrestore(&asic->lock, flags);

	return 0;
@@ -295,11 +308,12 @@ static struct irq_chip asic3_irq_chip = { 
	.unmask		= asic3_unmask_irq,

};



static int asic3_irq_probe(struct platform_device *pdev)

static int __init asic3_irq_probe(struct platform_device *pdev)

{

	struct asic3 *asic = platform_get_drvdata(pdev);

	unsigned long clksel = 0;

	unsigned int irq, irq_base;

	int map_size;



	asic->irq_nr = platform_get_irq(pdev, 0);

	if (asic->irq_nr < 0)
@@ -323,7 +337,7 @@ static int asic3_irq_probe(struct platform_device *pdev) 
		set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);

	}



	asic3_write_register(asic, ASIC3_OFFSET(INTR, IntMask),

	asic3_write_register(asic, ASIC3_OFFSET(INTR, INT_MASK),

			     ASIC3_INTMASK_GINTMASK);



	set_irq_chained_handler(asic->irq_nr, asic3_irq_demux);
@@ -350,149 +364,182 @@ static void asic3_irq_remove(struct platform_device *pdev) 
}



/* GPIOs */

static inline u32 asic3_get_gpio(struct asic3 *asic, unsigned int base,

				 unsigned int function)

{

	return asic3_read_register(asic, base + function);

}



static void asic3_set_gpio(struct asic3 *asic, unsigned int base,

			   unsigned int function, u32 bits, u32 val)

static int asic3_gpio_direction(struct gpio_chip *chip,

				unsigned offset, int out)

{

	u32 mask = ASIC3_GPIO_TO_MASK(offset), out_reg;

	unsigned int gpio_base;

	unsigned long flags;

	struct asic3 *asic;



	asic = container_of(chip, struct asic3, gpio);

	gpio_base = ASIC3_GPIO_TO_BASE(offset);



	if (gpio_base > ASIC3_GPIO_D_BASE) {

		dev_err(asic->dev, "Invalid base (0x%x) for gpio %d\n",

			gpio_base, offset);

		return -EINVAL;

	}



	spin_lock_irqsave(&asic->lock, flags);

	val |= (asic3_read_register(asic, base + function) & ~bits);



	asic3_write_register(asic, base + function, val);

	out_reg = asic3_read_register(asic, gpio_base + ASIC3_GPIO_DIRECTION);



	/* Input is 0, Output is 1 */

	if (out)

		out_reg |= mask;

	else

		out_reg &= ~mask;



	asic3_write_register(asic, gpio_base + ASIC3_GPIO_DIRECTION, out_reg);



	spin_unlock_irqrestore(&asic->lock, flags);



	return 0;



}



static int asic3_gpio_direction_input(struct gpio_chip *chip,

				      unsigned offset)

{

	return asic3_gpio_direction(chip, offset, 0);

}



static int asic3_gpio_direction_output(struct gpio_chip *chip,

				       unsigned offset, int value)

{

	return asic3_gpio_direction(chip, offset, 1);

}



#define asic3_get_gpio_a(asic, fn) \

	asic3_get_gpio(asic, ASIC3_GPIO_A_Base, ASIC3_GPIO_##fn)

#define asic3_get_gpio_b(asic, fn) \

	asic3_get_gpio(asic, ASIC3_GPIO_B_Base, ASIC3_GPIO_##fn)

#define asic3_get_gpio_c(asic, fn) \

	asic3_get_gpio(asic, ASIC3_GPIO_C_Base, ASIC3_GPIO_##fn)

#define asic3_get_gpio_d(asic, fn) \

	asic3_get_gpio(asic, ASIC3_GPIO_D_Base, ASIC3_GPIO_##fn)



#define asic3_set_gpio_a(asic, fn, bits, val) \

	asic3_set_gpio(asic, ASIC3_GPIO_A_Base, ASIC3_GPIO_##fn, bits, val)

#define asic3_set_gpio_b(asic, fn, bits, val) \

	asic3_set_gpio(asic, ASIC3_GPIO_B_Base, ASIC3_GPIO_##fn, bits, val)

#define asic3_set_gpio_c(asic, fn, bits, val) \

	asic3_set_gpio(asic, ASIC3_GPIO_C_Base, ASIC3_GPIO_##fn, bits, val)

#define asic3_set_gpio_d(asic, fn, bits, val) \

	asic3_set_gpio(asic, ASIC3_GPIO_D_Base, ASIC3_GPIO_##fn, bits, val)



#define asic3_set_gpio_banks(asic, fn, bits, pdata, field) 		  \

	do {								  \

	     asic3_set_gpio_a((asic), fn, (bits), (pdata)->gpio_a.field); \

	     asic3_set_gpio_b((asic), fn, (bits), (pdata)->gpio_b.field); \

	     asic3_set_gpio_c((asic), fn, (bits), (pdata)->gpio_c.field); \

	     asic3_set_gpio_d((asic), fn, (bits), (pdata)->gpio_d.field); \

	} while (0)



int asic3_gpio_get_value(struct asic3 *asic, unsigned gpio)

static int asic3_gpio_get(struct gpio_chip *chip,

			  unsigned offset)

{

	u32 mask = ASIC3_GPIO_bit(gpio);



	switch (gpio >> 4) {

	case ASIC3_GPIO_BANK_A:

		return asic3_get_gpio_a(asic, Status) & mask;

	case ASIC3_GPIO_BANK_B:

		return asic3_get_gpio_b(asic, Status) & mask;

	case ASIC3_GPIO_BANK_C:

		return asic3_get_gpio_c(asic, Status) & mask;

	case ASIC3_GPIO_BANK_D:

		return asic3_get_gpio_d(asic, Status) & mask;

	default:

		printk(KERN_ERR "%s: invalid GPIO value 0x%x",

		       __func__, gpio);

	unsigned int gpio_base;

	u32 mask = ASIC3_GPIO_TO_MASK(offset);

	struct asic3 *asic;



	asic = container_of(chip, struct asic3, gpio);

	gpio_base = ASIC3_GPIO_TO_BASE(offset);



	if (gpio_base > ASIC3_GPIO_D_BASE) {

		dev_err(asic->dev, "Invalid base (0x%x) for gpio %d\n",

			gpio_base, offset);

		return -EINVAL;

	}



	return asic3_read_register(asic, gpio_base + ASIC3_GPIO_STATUS) & mask;

}

EXPORT_SYMBOL(asic3_gpio_get_value);



void asic3_gpio_set_value(struct asic3 *asic, unsigned gpio, int val)

static void asic3_gpio_set(struct gpio_chip *chip,

			   unsigned offset, int value)

{

	u32 mask = ASIC3_GPIO_bit(gpio);

	u32 bitval = 0;

	if (val)

		bitval = mask;



	switch (gpio >> 4) {

	case ASIC3_GPIO_BANK_A:

		asic3_set_gpio_a(asic, Out, mask, bitval);

		return;

	case ASIC3_GPIO_BANK_B:

		asic3_set_gpio_b(asic, Out, mask, bitval);

		return;

	case ASIC3_GPIO_BANK_C:

		asic3_set_gpio_c(asic, Out, mask, bitval);

		return;

	case ASIC3_GPIO_BANK_D:

		asic3_set_gpio_d(asic, Out, mask, bitval);

		return;

	default:

		printk(KERN_ERR "%s: invalid GPIO value 0x%x",

		       __func__, gpio);

	u32 mask, out_reg;

	unsigned int gpio_base;

	unsigned long flags;

	struct asic3 *asic;



	asic = container_of(chip, struct asic3, gpio);

	gpio_base = ASIC3_GPIO_TO_BASE(offset);



	if (gpio_base > ASIC3_GPIO_D_BASE) {

		dev_err(asic->dev, "Invalid base (0x%x) for gpio %d\n",

			gpio_base, offset);

		return;

	}



	mask = ASIC3_GPIO_TO_MASK(offset);



	spin_lock_irqsave(&asic->lock, flags);



	out_reg = asic3_read_register(asic, gpio_base + ASIC3_GPIO_OUT);



	if (value)

		out_reg |= mask;

	else

		out_reg &= ~mask;



	asic3_write_register(asic, gpio_base + ASIC3_GPIO_OUT, out_reg);



	spin_unlock_irqrestore(&asic->lock, flags);



	return;

}

EXPORT_SYMBOL(asic3_gpio_set_value);



static int asic3_gpio_probe(struct platform_device *pdev)

static __init int asic3_gpio_probe(struct platform_device *pdev,

				   u16 *gpio_config, int num)

{

	struct asic3_platform_data *pdata = pdev->dev.platform_data;

	struct asic3 *asic = platform_get_drvdata(pdev);

	u16 alt_reg[ASIC3_NUM_GPIO_BANKS];

	u16 out_reg[ASIC3_NUM_GPIO_BANKS];

	u16 dir_reg[ASIC3_NUM_GPIO_BANKS];

	int i;



	memzero(alt_reg, ASIC3_NUM_GPIO_BANKS * sizeof(u16));

	memzero(out_reg, ASIC3_NUM_GPIO_BANKS * sizeof(u16));

	memzero(dir_reg, ASIC3_NUM_GPIO_BANKS * sizeof(u16));



	/* Enable all GPIOs */

	asic3_write_register(asic, ASIC3_GPIO_OFFSET(A, MASK), 0xffff);

	asic3_write_register(asic, ASIC3_GPIO_OFFSET(B, MASK), 0xffff);

	asic3_write_register(asic, ASIC3_GPIO_OFFSET(C, MASK), 0xffff);

	asic3_write_register(asic, ASIC3_GPIO_OFFSET(D, MASK), 0xffff);



	for (i = 0; i < num; i++) {

		u8 alt, pin, dir, init, bank_num, bit_num;

		u16 config = gpio_config[i];



		pin = ASIC3_CONFIG_GPIO_PIN(config);

		alt = ASIC3_CONFIG_GPIO_ALT(config);

		dir = ASIC3_CONFIG_GPIO_DIR(config);

		init = ASIC3_CONFIG_GPIO_INIT(config);



	asic3_write_register(asic, ASIC3_GPIO_OFFSET(A, Mask), 0xffff);

	asic3_write_register(asic, ASIC3_GPIO_OFFSET(B, Mask), 0xffff);

	asic3_write_register(asic, ASIC3_GPIO_OFFSET(C, Mask), 0xffff);

	asic3_write_register(asic, ASIC3_GPIO_OFFSET(D, Mask), 0xffff);



	asic3_set_gpio_a(asic, SleepMask, 0xffff, 0xffff);

	asic3_set_gpio_b(asic, SleepMask, 0xffff, 0xffff);

	asic3_set_gpio_c(asic, SleepMask, 0xffff, 0xffff);

	asic3_set_gpio_d(asic, SleepMask, 0xffff, 0xffff);



	if (pdata) {

		asic3_set_gpio_banks(asic, Out, 0xffff, pdata, init);

		asic3_set_gpio_banks(asic, Direction, 0xffff, pdata, dir);

		asic3_set_gpio_banks(asic, SleepMask, 0xffff, pdata,

				     sleep_mask);

		asic3_set_gpio_banks(asic, SleepOut, 0xffff, pdata, sleep_out);

		asic3_set_gpio_banks(asic, BattFaultOut, 0xffff, pdata,

				     batt_fault_out);

		asic3_set_gpio_banks(asic, SleepConf, 0xffff, pdata,

				     sleep_conf);

		asic3_set_gpio_banks(asic, AltFunction, 0xffff, pdata,

				     alt_function);

		bank_num = ASIC3_GPIO_TO_BANK(pin);

		bit_num = ASIC3_GPIO_TO_BIT(pin);



		alt_reg[bank_num] |= (alt << bit_num);

		out_reg[bank_num] |= (init << bit_num);

		dir_reg[bank_num] |= (dir << bit_num);

	}



	return 0;

	for (i = 0; i < ASIC3_NUM_GPIO_BANKS; i++) {

		asic3_write_register(asic,

				     ASIC3_BANK_TO_BASE(i) +

				     ASIC3_GPIO_DIRECTION,

				     dir_reg[i]);

		asic3_write_register(asic,

				     ASIC3_BANK_TO_BASE(i) + ASIC3_GPIO_OUT,

				     out_reg[i]);

		asic3_write_register(asic,

				     ASIC3_BANK_TO_BASE(i) +

				     ASIC3_GPIO_ALT_FUNCTION,

				     alt_reg[i]);

	}



	return gpiochip_add(&asic->gpio);

}



static void asic3_gpio_remove(struct platform_device *pdev)

static int asic3_gpio_remove(struct platform_device *pdev)

{

	return;

	struct asic3 *asic = platform_get_drvdata(pdev);



	return gpiochip_remove(&asic->gpio);

}





/* Core */

static int asic3_probe(struct platform_device *pdev)

static int __init asic3_probe(struct platform_device *pdev)

{

	struct asic3_platform_data *pdata = pdev->dev.platform_data;

	struct asic3 *asic;

	struct resource *mem;

	unsigned long clksel;

	int ret;

	int ret = 0;



	asic = kzalloc(sizeof(struct asic3), GFP_KERNEL);

	if (!asic)

	if (asic == NULL) {

		printk(KERN_ERR "kzalloc failed\n");

		return -ENOMEM;

	}



	spin_lock_init(&asic->lock);

	platform_set_drvdata(pdev, asic);
@@ -501,49 +548,58 @@ static int asic3_probe(struct platform_device *pdev) 
	mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);

	if (!mem) {

		ret = -ENOMEM;

		printk(KERN_ERR "asic3: no MEM resource\n");

		goto err_out_1;

		dev_err(asic->dev, "no MEM resource\n");

		goto out_free;

	}



	asic->mapping = ioremap(mem->start, PAGE_SIZE);

	map_size = mem->end - mem->start + 1;

	asic->mapping = ioremap(mem->start, map_size);

	if (!asic->mapping) {

		ret = -ENOMEM;

		printk(KERN_ERR "asic3: couldn't ioremap\n");

		goto err_out_1;

		dev_err(asic->dev, "Couldn't ioremap\n");

		goto out_free;

	}



	asic->irq_base = pdata->irq_base;



	if (pdata && pdata->bus_shift)

		asic->bus_shift = 2 - pdata->bus_shift;

	else

		asic->bus_shift = 0;

	/* calculate bus shift from mem resource */

	asic->bus_shift = 2 - (map_size >> 12);



	clksel = 0;

	asic3_write_register(asic, ASIC3_OFFSET(CLOCK, SEL), clksel);



	ret = asic3_irq_probe(pdev);

	if (ret < 0) {

		printk(KERN_ERR "asic3: couldn't probe IRQs\n");

		goto err_out_2;

		dev_err(asic->dev, "Couldn't probe IRQs\n");

		goto out_unmap;

	}

	asic3_gpio_probe(pdev);



	if (pdata->children) {

		int i;

		for (i = 0; i < pdata->n_children; i++) {

			pdata->children[i]->dev.parent = &pdev->dev;

			platform_device_register(pdata->children[i]);

		}

	asic->gpio.base = pdata->gpio_base;

	asic->gpio.ngpio = ASIC3_NUM_GPIOS;

	asic->gpio.get = asic3_gpio_get;

	asic->gpio.set = asic3_gpio_set;

	asic->gpio.direction_input = asic3_gpio_direction_input;

	asic->gpio.direction_output = asic3_gpio_direction_output;



	ret = asic3_gpio_probe(pdev,

			       pdata->gpio_config,

			       pdata->gpio_config_num);

	if (ret < 0) {

		dev_err(asic->dev, "GPIO probe failed\n");

		goto out_irq;

	}



	printk(KERN_INFO "ASIC3 Core driver\n");

	dev_info(asic->dev, "ASIC3 Core driver\n");



	return 0;



 err_out_2:

 out_irq:

	asic3_irq_remove(pdev);



 out_unmap:

	iounmap(asic->mapping);

 err_out_1:



 out_free:

	kfree(asic);



	return ret;
@@ -551,9 +607,12 @@ static int asic3_probe(struct platform_device *pdev) 


static int asic3_remove(struct platform_device *pdev)

{

	int ret;

	struct asic3 *asic = platform_get_drvdata(pdev);



	asic3_gpio_remove(pdev);

	ret = asic3_gpio_remove(pdev);

	if (ret < 0)

		return ret;

	asic3_irq_remove(pdev);



	asic3_write_register(asic, ASIC3_OFFSET(CLOCK, SEL), 0);
@@ -573,7 +632,6 @@ static struct platform_driver asic3_device_driver = { 
	.driver		= {

		.name	= "asic3",

	},

	.probe		= asic3_probe,

	.remove		= __devexit_p(asic3_remove),

	.shutdown	= asic3_shutdown,

};
@@ -581,7 +639,7 @@ static struct platform_driver asic3_device_driver = { 
static int __init asic3_init(void)

{

	int retval = 0;

	retval = platform_driver_register(&asic3_device_driver);

	retval = platform_driver_probe(&asic3_device_driver, asic3_probe);

	return retval;

}

include/linux/mfd/asic3.h

+95 −90

File changed.

Preview size limit exceeded, changes collapsed.

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