Commit adf151c2 authored by Jordan Crouse's avatar Jordan Crouse Committed by Rob Clark
Browse files

drm/msm/adreno: Enable 64 bit mode by default on a5xx and a6xx targets 



A5XX and newer GPUs can be run in either 32 or 64 bit mode. The GPU
registers and the microcode use 64 bit virtual addressing in either
case but the upper 32 bits are ignored if the GPU is in 32 bit mode.
There is no performance disadvantage to remaining in 64 bit mode even
if we are only generating 32 bit addresses so switch over now to prepare
for using addresses above 4G on targets that support them.

Signed-off-by: default avatarJordan Crouse <jcrouse@codeaurora.org>
Signed-off-by: default avatarRob Clark <robdclark@chromium.org>
parent c8bffdcb

drivers/gpu/drm/msm/adreno/a5xx_gpu.c

+14 −0
Original line number Diff line number Diff line
@@ -642,6 +642,20 @@ static int a5xx_hw_init(struct msm_gpu *gpu) 
		REG_A5XX_RBBM_SECVID_TSB_TRUSTED_BASE_HI, 0x00000000);

	gpu_write(gpu, REG_A5XX_RBBM_SECVID_TSB_TRUSTED_SIZE, 0x00000000);



	/* Put the GPU into 64 bit by default */

	gpu_write(gpu, REG_A5XX_CP_ADDR_MODE_CNTL, 0x1);

	gpu_write(gpu, REG_A5XX_VSC_ADDR_MODE_CNTL, 0x1);

	gpu_write(gpu, REG_A5XX_GRAS_ADDR_MODE_CNTL, 0x1);

	gpu_write(gpu, REG_A5XX_RB_ADDR_MODE_CNTL, 0x1);

	gpu_write(gpu, REG_A5XX_PC_ADDR_MODE_CNTL, 0x1);

	gpu_write(gpu, REG_A5XX_HLSQ_ADDR_MODE_CNTL, 0x1);

	gpu_write(gpu, REG_A5XX_VFD_ADDR_MODE_CNTL, 0x1);

	gpu_write(gpu, REG_A5XX_VPC_ADDR_MODE_CNTL, 0x1);

	gpu_write(gpu, REG_A5XX_UCHE_ADDR_MODE_CNTL, 0x1);

	gpu_write(gpu, REG_A5XX_SP_ADDR_MODE_CNTL, 0x1);

	gpu_write(gpu, REG_A5XX_TPL1_ADDR_MODE_CNTL, 0x1);

	gpu_write(gpu, REG_A5XX_RBBM_SECVID_TSB_ADDR_MODE_CNTL, 0x1);



	ret = adreno_hw_init(gpu);

	if (ret)

		return ret;

drivers/gpu/drm/msm/adreno/a6xx_gpu.c

+14 −0
Original line number Diff line number Diff line
@@ -391,6 +391,20 @@ static int a6xx_hw_init(struct msm_gpu *gpu) 
		REG_A6XX_RBBM_SECVID_TSB_TRUSTED_BASE_HI, 0x00000000);

	gpu_write(gpu, REG_A6XX_RBBM_SECVID_TSB_TRUSTED_SIZE, 0x00000000);



	/* Turn on 64 bit addressing for all blocks */

	gpu_write(gpu, REG_A6XX_CP_ADDR_MODE_CNTL, 0x1);

	gpu_write(gpu, REG_A6XX_VSC_ADDR_MODE_CNTL, 0x1);

	gpu_write(gpu, REG_A6XX_GRAS_ADDR_MODE_CNTL, 0x1);

	gpu_write(gpu, REG_A6XX_RB_ADDR_MODE_CNTL, 0x1);

	gpu_write(gpu, REG_A6XX_PC_ADDR_MODE_CNTL, 0x1);

	gpu_write(gpu, REG_A6XX_HLSQ_ADDR_MODE_CNTL, 0x1);

	gpu_write(gpu, REG_A6XX_VFD_ADDR_MODE_CNTL, 0x1);

	gpu_write(gpu, REG_A6XX_VPC_ADDR_MODE_CNTL, 0x1);

	gpu_write(gpu, REG_A6XX_UCHE_ADDR_MODE_CNTL, 0x1);

	gpu_write(gpu, REG_A6XX_SP_ADDR_MODE_CNTL, 0x1);

	gpu_write(gpu, REG_A6XX_TPL1_ADDR_MODE_CNTL, 0x1);

	gpu_write(gpu, REG_A6XX_RBBM_SECVID_TSB_ADDR_MODE_CNTL, 0x1);



	/* enable hardware clockgating */

	a6xx_set_hwcg(gpu, true);

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