Commit adcbc921 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'drm-fixes-2019-02-08' of git://anongit.freedesktop.org/drm/drm 

Pull drm fixes from Dave Airlie:
 "Missed fixes last week as had nothing until amdgpu showed up on
  Saturday. Other stuff has since rolled in along with some more amdgpu
  fixes, so we have two weeks of those, and some i915, vmwgfx, sun4i,
  rockchip and omap fixes.

  amdgpu/radeon:
   - fix crash on passthrough for SI
   - fencing fix for shared buffers
   - APU hwmon fix
   - API powerplay fix
   - eDP freesync fix
   - PASID mgr locking fix
   - KFD warning fix
   - DC/powerplay fix
   - raven revision ids fix
   - vega20 doorbell fix

  i915:
   - SNB display fix
   - SKL srckey mask fix
   - ICL DDI clock selection fix

  vmwgfx:
   - DMA API fix
   - IOMMU detection fix
   - display fixes

  sun4i:
   - tcon clock fix

  rockchip:
   - SPDX identifier fix

  omap:
   - DSI fixes"

* tag 'drm-fixes-2019-02-08' of git://anongit.freedesktop.org/drm/drm: (28 commits)
  drm/omap: dsi: Hack-fix DSI bus flags
  drm/omap: dsi: Fix OF platform depopulate
  drm/omap: dsi: Fix crash in DSI debug dumps
  drm/i915: Try to sanitize bogus DPLL state left over by broken SNB BIOSen
  drm/amd/display: Attach VRR properties for eDP connectors
  drm/amdkfd: Fix if preprocessor statement above kfd_fill_iolink_info_for_cpu
  drm/amdgpu: use spin_lock_irqsave to protect vm_manager.pasid_idr
  drm/i915: always return something on DDI clock selection
  drm/i915: Fix skl srckey mask bits
  drm/vmwgfx: Improve on IOMMU detection
  drm/vmwgfx: Fix setting of dma masks
  drm/vmwgfx: Also check for crtc status while checking for DU active
  drm/vmwgfx: Fix an uninitialized fence handle value
  drm/vmwgfx: Return error code from vmw_execbuf_copy_fence_user
  drm/sun4i: tcon: Prepare and enable TCON channel 0 clock at init
  drm/amdgpu: fix the incorrect external id for raven series
  drm/amdgpu: Implement doorbell self-ring for NBIO 7.4
  drm/amd/display: Fix fclk idle state
  drm/amdgpu: Transfer fences to dmabuf importer
  drm/amd/powerplay: Fix missing break in switch
  ...
parents 74e96711 dada163c

drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c

+2 −1
Original line number Diff line number Diff line
@@ -1686,7 +1686,8 @@ static umode_t hwmon_attributes_visible(struct kobject *kobj, 
		effective_mode &= ~S_IWUSR;



	if ((adev->flags & AMD_IS_APU) &&

	    (attr == &sensor_dev_attr_power1_cap_max.dev_attr.attr ||

	    (attr == &sensor_dev_attr_power1_average.dev_attr.attr ||

	     attr == &sensor_dev_attr_power1_cap_max.dev_attr.attr ||

	     attr == &sensor_dev_attr_power1_cap_min.dev_attr.attr||

	     attr == &sensor_dev_attr_power1_cap.dev_attr.attr))

		return 0;

drivers/gpu/drm/amd/amdgpu/amdgpu_prime.c

+51 −8
Original line number Diff line number Diff line
@@ -38,6 +38,7 @@ 
#include "amdgpu_gem.h"

#include <drm/amdgpu_drm.h>

#include <linux/dma-buf.h>

#include <linux/dma-fence-array.h>



/**

 * amdgpu_gem_prime_get_sg_table - &drm_driver.gem_prime_get_sg_table
@@ -187,6 +188,48 @@ error: 
	return ERR_PTR(ret);

}



static int

__reservation_object_make_exclusive(struct reservation_object *obj)

{

	struct dma_fence **fences;

	unsigned int count;

	int r;



	if (!reservation_object_get_list(obj)) /* no shared fences to convert */

		return 0;



	r = reservation_object_get_fences_rcu(obj, NULL, &count, &fences);

	if (r)

		return r;



	if (count == 0) {

		/* Now that was unexpected. */

	} else if (count == 1) {

		reservation_object_add_excl_fence(obj, fences[0]);

		dma_fence_put(fences[0]);

		kfree(fences);

	} else {

		struct dma_fence_array *array;



		array = dma_fence_array_create(count, fences,

					       dma_fence_context_alloc(1), 0,

					       false);

		if (!array)

			goto err_fences_put;



		reservation_object_add_excl_fence(obj, &array->base);

		dma_fence_put(&array->base);

	}



	return 0;



err_fences_put:

	while (count--)

		dma_fence_put(fences[count]);

	kfree(fences);

	return -ENOMEM;

}



/**

 * amdgpu_gem_map_attach - &dma_buf_ops.attach implementation

 * @dma_buf: Shared DMA buffer
@@ -218,17 +261,17 @@ static int amdgpu_gem_map_attach(struct dma_buf *dma_buf, 


	if (attach->dev->driver != adev->dev->driver) {

		/*

		 * Wait for all shared fences to complete before we switch to future

		 * use of exclusive fence on this prime shared bo.

		 * We only create shared fences for internal use, but importers

		 * of the dmabuf rely on exclusive fences for implicitly

		 * tracking write hazards. As any of the current fences may

		 * correspond to a write, we need to convert all existing

		 * fences on the reservation object into a single exclusive

		 * fence.

		 */

		r = reservation_object_wait_timeout_rcu(bo->tbo.resv,

							true, false,

							MAX_SCHEDULE_TIMEOUT);

		if (unlikely(r < 0)) {

			DRM_DEBUG_PRIME("Fence wait failed: %li\n", r);

		r = __reservation_object_make_exclusive(bo->tbo.resv);

		if (r)

			goto error_unreserve;

	}

	}



	/* pin buffer into GTT */

	r = amdgpu_bo_pin(bo, AMDGPU_GEM_DOMAIN_GTT);

drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c

+3 −2
Original line number Diff line number Diff line
@@ -3363,14 +3363,15 @@ void amdgpu_vm_get_task_info(struct amdgpu_device *adev, unsigned int pasid, 
			 struct amdgpu_task_info *task_info)

{

	struct amdgpu_vm *vm;

	unsigned long flags;



	spin_lock(&adev->vm_manager.pasid_lock);

	spin_lock_irqsave(&adev->vm_manager.pasid_lock, flags);



	vm = idr_find(&adev->vm_manager.pasid_idr, pasid);

	if (vm)

		*task_info = vm->task_info;



	spin_unlock(&adev->vm_manager.pasid_lock);

	spin_unlock_irqrestore(&adev->vm_manager.pasid_lock, flags);

}



/**

drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c

+13 −0
Original line number Diff line number Diff line
@@ -93,7 +93,20 @@ static void nbio_v7_4_enable_doorbell_aperture(struct amdgpu_device *adev, 
static void nbio_v7_4_enable_doorbell_selfring_aperture(struct amdgpu_device *adev,

							bool enable)

{

	u32 tmp = 0;



	if (enable) {

		tmp = REG_SET_FIELD(tmp, DOORBELL_SELFRING_GPA_APER_CNTL, DOORBELL_SELFRING_GPA_APER_EN, 1) |

		      REG_SET_FIELD(tmp, DOORBELL_SELFRING_GPA_APER_CNTL, DOORBELL_SELFRING_GPA_APER_MODE, 1) |

		      REG_SET_FIELD(tmp, DOORBELL_SELFRING_GPA_APER_CNTL, DOORBELL_SELFRING_GPA_APER_SIZE, 0);



		WREG32_SOC15(NBIO, 0, mmDOORBELL_SELFRING_GPA_APER_BASE_LOW,

			     lower_32_bits(adev->doorbell.base));

		WREG32_SOC15(NBIO, 0, mmDOORBELL_SELFRING_GPA_APER_BASE_HIGH,

			     upper_32_bits(adev->doorbell.base));

	}



	WREG32_SOC15(NBIO, 0, mmDOORBELL_SELFRING_GPA_APER_CNTL, tmp);

}



static void nbio_v7_4_ih_doorbell_range(struct amdgpu_device *adev,

drivers/gpu/drm/amd/amdgpu/soc15.c

+4 −2
Original line number Diff line number Diff line
@@ -729,11 +729,13 @@ static int soc15_common_early_init(void *handle) 
	case CHIP_RAVEN:

		adev->asic_funcs = &soc15_asic_funcs;

		if (adev->rev_id >= 0x8)

			adev->external_rev_id = adev->rev_id + 0x81;

			adev->external_rev_id = adev->rev_id + 0x79;

		else if (adev->pdev->device == 0x15d8)

			adev->external_rev_id = adev->rev_id + 0x41;

		else if (adev->rev_id == 1)

			adev->external_rev_id = adev->rev_id + 0x20;

		else

			adev->external_rev_id = 0x1;

			adev->external_rev_id = adev->rev_id + 0x01;



		if (adev->rev_id >= 0x8) {

			adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |

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