drm/i915: Pass intel_gt to intel_engines_init_mmio

struct drm_printer;

struct intel_gt;

/* Early gen2 devices have a cacheline of just 32 bytes, using 64 is overkill,

 * but keeps the logic simple. Indeed, the whole purpose of this macro is just

 * to give some inclination as to some of the magic values used in the various

	return (head - tail - CACHELINE_BYTES) & (size - 1);

}

int intel_engines_init_mmio(struct drm_i915_private *i915);

int intel_engines_init_mmio(struct intel_gt *gt);

int intel_engines_setup(struct drm_i915_private *i915);

int intel_engines_init(struct drm_i915_private *i915);

void intel_engines_cleanup(struct drm_i915_private *i915);

/**

 * intel_engines_init_mmio() - allocate and prepare the Engine Command Streamers

 * @i915: the i915 device

 * @gt: pointer to struct intel_gt

 *

 * Return: non-zero if the initialization failed.

 */

int intel_engines_init_mmio(struct drm_i915_private *i915)

int intel_engines_init_mmio(struct intel_gt *gt)

{

	struct drm_i915_private *i915 = gt->i915;

	struct intel_device_info *device_info = mkwrite_device_info(i915);

	const unsigned int engine_mask = INTEL_INFO(i915)->engine_mask;

	unsigned int mask = 0;

		if (!HAS_ENGINE(i915, i))

			continue;

		err = intel_engine_setup(&i915->gt, i);

		err = intel_engine_setup(gt, i);

		if (err)

			goto cleanup;

	RUNTIME_INFO(i915)->num_engines = hweight32(mask);

	intel_gt_check_and_clear_faults(&i915->gt);

	intel_gt_check_and_clear_faults(gt);

	intel_setup_engine_capabilities(i915);

	intel_uc_init_mmio(&dev_priv->gt.uc);

	ret = intel_engines_init_mmio(dev_priv);

	ret = intel_engines_init_mmio(&dev_priv->gt);

	if (ret)

		goto err_uncore;