Commit adbb78e1 authored by Ulrich Hecht's avatar Ulrich Hecht Committed by Simon Horman
Browse files

ARM: dts: r8a7778: Add HSCIF0/1 support 



Add HSCIF0/1 clocks and device nodes, based on Rev. 1.00 of the R-Car
M1A datasheet.

Signed-off-by: default avatarUlrich Hecht <ulrich.hecht+renesas@gmail.com>
[geert: Squashed two patches]
[geert: Correct HSCIF1 module clock index]
[geert: Correct reg properties for non-LPAE]
Signed-off-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: default avatarSimon Horman <horms+renesas@verge.net.au>
parent 383f6024

arch/arm/boot/dts/r8a7778.dtsi

+28 −0
Original line number Diff line number Diff line
@@ -367,6 +367,30 @@ 
		status = "disabled";

	};



	hscif0: serial@ffe48000 {

		compatible = "renesas,hscif-r8a7778",

			     "renesas,rcar-gen1-hscif", "renesas,hscif";

		reg = <0xffe48000 96>;

		interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;

		clocks = <&mstp0_clks R8A7778_CLK_HSCIF0>,

			 <&cpg_clocks R8A7778_CLK_S>, <&scif_clk>;

		clock-names = "fck", "brg_int", "scif_clk";

		power-domains = <&cpg_clocks>;

		status = "disabled";

	};



	hscif1: serial@ffe49000 {

		compatible = "renesas,hscif-r8a7778",

			     "renesas,rcar-gen1-hscif", "renesas,hscif";

		reg = <0xffe49000 96>;

		interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;

		clocks = <&mstp0_clks R8A7778_CLK_HSCIF1>,

			 <&cpg_clocks R8A7778_CLK_S>, <&scif_clk>;

		clock-names = "fck", "brg_int", "scif_clk";

		power-domains = <&cpg_clocks>;

		status = "disabled";

	};



	mmcif: mmc@ffe4e000 {

		compatible = "renesas,mmcif-r8a7778", "renesas,sh-mmcif";

		reg = <0xffe4e000 0x100>;
@@ -535,6 +559,8 @@ 
				 <&cpg_clocks R8A7778_CLK_P>,

				 <&cpg_clocks R8A7778_CLK_P>,

				 <&cpg_clocks R8A7778_CLK_P>,

				 <&cpg_clocks R8A7778_CLK_S>,

				 <&cpg_clocks R8A7778_CLK_S>,

				 <&cpg_clocks R8A7778_CLK_P>,

				 <&cpg_clocks R8A7778_CLK_P>,

				 <&cpg_clocks R8A7778_CLK_P>,
@@ -551,6 +577,7 @@ 
				R8A7778_CLK_SCIF0 R8A7778_CLK_SCIF1

				R8A7778_CLK_SCIF2 R8A7778_CLK_SCIF3

				R8A7778_CLK_SCIF4 R8A7778_CLK_SCIF5

				R8A7778_CLK_HSCIF0 R8A7778_CLK_HSCIF1

				R8A7778_CLK_TMU0 R8A7778_CLK_TMU1

				R8A7778_CLK_TMU2 R8A7778_CLK_SSI0

				R8A7778_CLK_SSI1 R8A7778_CLK_SSI2
@@ -560,6 +587,7 @@ 
			clock-output-names =

				"i2c0", "i2c1", "i2c2", "i2c3", "scif0",

				"scif1", "scif2", "scif3", "scif4", "scif5",

				"hscif0", "hscif1",

				"tmu0", "tmu1", "tmu2", "ssi0", "ssi1",

				"ssi2", "ssi3", "sru", "hspi";

		};

include/dt-bindings/clock/r8a7778-clock.h

+2 −0
Original line number Diff line number Diff line
@@ -30,6 +30,8 @@ 
#define R8A7778_CLK_SCIF3	23

#define R8A7778_CLK_SCIF4	22

#define R8A7778_CLK_SCIF5	21

#define R8A7778_CLK_HSCIF0	19

#define R8A7778_CLK_HSCIF1	18

#define R8A7778_CLK_TMU0	16

#define R8A7778_CLK_TMU1	15

#define R8A7778_CLK_TMU2	14

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