Commit adb37892 authored by Deng-Cheng Zhu's avatar Deng-Cheng Zhu Committed by Ralf Baechle
Browse files

MIPS: Fix ISA level which causes secondary cache init bypassing and more 



The commit a96102be introduced set_isa() where compatible ISA info is
also set aside from the one gets passed in. It means, for example, 1004K
will have MIPS_CPU_ISA_M32R2/M32R1/II/I flags. This leads to things like
the following inappropriate:

if (c->isa_level == MIPS_CPU_ISA_M32R1 ||
    c->isa_level == MIPS_CPU_ISA_M32R2 ||
    c->isa_level == MIPS_CPU_ISA_M64R1 ||
    c->isa_level == MIPS_CPU_ISA_M64R2)

This patch fixes it.

Signed-off-by: default avatarDeng-Cheng Zhu <dengcheng.zhu@imgtec.com>
Cc: Steven J. Hill <Steven.Hill@imgtec.com>
Cc: linux-mips@linux-mips.org
Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
parent ed1197f9

arch/mips/kernel/cpu-probe.c

+2 −4
Original line number Diff line number Diff line
@@ -1226,10 +1226,8 @@ __cpuinit void cpu_probe(void) 
	if (c->options & MIPS_CPU_FPU) {

		c->fpu_id = cpu_get_fpu_id();



		if (c->isa_level == MIPS_CPU_ISA_M32R1 ||

		    c->isa_level == MIPS_CPU_ISA_M32R2 ||

		    c->isa_level == MIPS_CPU_ISA_M64R1 ||

		    c->isa_level == MIPS_CPU_ISA_M64R2) {

		if (c->isa_level & (MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M32R2 |

				    MIPS_CPU_ISA_M64R1 | MIPS_CPU_ISA_M64R2)) {

			if (c->fpu_id & MIPS_FPIR_3D)

				c->ases |= MIPS_ASE_MIPS3D;

		}

arch/mips/kernel/traps.c

+1 −1
Original line number Diff line number Diff line
@@ -1571,7 +1571,7 @@ void __cpuinit per_cpu_trap_init(bool is_boot_cpu) 
#ifdef CONFIG_64BIT

	status_set |= ST0_FR|ST0_KX|ST0_SX|ST0_UX;

#endif

	if (current_cpu_data.isa_level == MIPS_CPU_ISA_IV)

	if (current_cpu_data.isa_level & MIPS_CPU_ISA_IV)

		status_set |= ST0_XX;

	if (cpu_has_dsp)

		status_set |= ST0_MX;

arch/mips/mm/c-r4k.c

+2 −4
Original line number Diff line number Diff line
@@ -1247,10 +1247,8 @@ static void __cpuinit setup_scache(void) 
		return;



	default:

		if (c->isa_level == MIPS_CPU_ISA_M32R1 ||

		    c->isa_level == MIPS_CPU_ISA_M32R2 ||

		    c->isa_level == MIPS_CPU_ISA_M64R1 ||

		    c->isa_level == MIPS_CPU_ISA_M64R2) {

		if (c->isa_level & (MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M32R2 |

				    MIPS_CPU_ISA_M64R1 | MIPS_CPU_ISA_M64R2)) {

#ifdef CONFIG_MIPS_CPU_SCACHE

			if (mips_sc_init ()) {

				scache_size = c->scache.ways * c->scache.sets * c->scache.linesz;

arch/mips/mm/sc-mips.c

+2 −4
Original line number Diff line number Diff line
@@ -98,10 +98,8 @@ static inline int __init mips_sc_probe(void) 
	c->scache.flags |= MIPS_CACHE_NOT_PRESENT;



	/* Ignore anything but MIPSxx processors */

	if (c->isa_level != MIPS_CPU_ISA_M32R1 &&

	    c->isa_level != MIPS_CPU_ISA_M32R2 &&

	    c->isa_level != MIPS_CPU_ISA_M64R1 &&

	    c->isa_level != MIPS_CPU_ISA_M64R2)

	if (!(c->isa_level & (MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M32R2 |

			      MIPS_CPU_ISA_M64R1 | MIPS_CPU_ISA_M64R2)))

		return 0;



	/* Does this MIPS32/MIPS64 CPU have a config2 register? */

CRA Git | Maintained and supported by SUSTech CRA and CCSE