Commit ad9a5b78 authored by Christian König's avatar Christian König Committed by Alex Deucher
Browse files

drm/amdgpu: correctly sign extend 48bit addresses v3 



Correct sign extend the GMC addresses to 48bit.

v2: sign extending turned out easier than thought.
v3: clean up the defines and move them into amdgpu_gmc.h as well

Signed-off-by: default avatarChristian König <christian.koenig@amd.com>
Reviewed-by: default avatarJunwei Zhang <Jerry.Zhang@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent bcdc9fd6

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c

+1 −1
Original line number Diff line number Diff line
@@ -135,7 +135,7 @@ void amdgpu_amdkfd_device_init(struct amdgpu_device *adev) 
			.num_queue_per_pipe = adev->gfx.mec.num_queue_per_pipe,

			.gpuvm_size = min(adev->vm_manager.max_pfn

					  << AMDGPU_GPU_PAGE_SHIFT,

					  AMDGPU_VA_HOLE_START),

					  AMDGPU_GMC_HOLE_START),

			.drm_render_minor = adev->ddev->render->index

		};

drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c

+1 −1
Original line number Diff line number Diff line
@@ -835,7 +835,7 @@ static int amdgpu_cs_vm_handling(struct amdgpu_cs_parser *p) 
			if (chunk->chunk_id != AMDGPU_CHUNK_ID_IB)

				continue;



			va_start = chunk_ib->va_start & AMDGPU_VA_HOLE_MASK;

			va_start = chunk_ib->va_start & AMDGPU_GMC_HOLE_MASK;

			r = amdgpu_cs_find_mapping(p, va_start, &aobj, &m);

			if (r) {

				DRM_ERROR("IB va_start is invalid\n");

drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c

+5 −5
Original line number Diff line number Diff line
@@ -572,16 +572,16 @@ int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data, 
		return -EINVAL;

	}



	if (args->va_address >= AMDGPU_VA_HOLE_START &&

	    args->va_address < AMDGPU_VA_HOLE_END) {

	if (args->va_address >= AMDGPU_GMC_HOLE_START &&

	    args->va_address < AMDGPU_GMC_HOLE_END) {

		dev_dbg(&dev->pdev->dev,

			"va_address 0x%LX is in VA hole 0x%LX-0x%LX\n",

			args->va_address, AMDGPU_VA_HOLE_START,

			AMDGPU_VA_HOLE_END);

			args->va_address, AMDGPU_GMC_HOLE_START,

			AMDGPU_GMC_HOLE_END);

		return -EINVAL;

	}



	args->va_address &= AMDGPU_VA_HOLE_MASK;

	args->va_address &= AMDGPU_GMC_HOLE_MASK;



	if ((args->flags & ~valid_flags) && (args->flags & ~prt_flags)) {

		dev_dbg(&dev->pdev->dev, "invalid flags combination 0x%08X\n",

drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h

+26 −0
Original line number Diff line number Diff line
@@ -30,6 +30,19 @@ 


#include "amdgpu_irq.h"



/* VA hole for 48bit addresses on Vega10 */

#define AMDGPU_GMC_HOLE_START	0x0000800000000000ULL

#define AMDGPU_GMC_HOLE_END	0xffff800000000000ULL



/*

 * Hardware is programmed as if the hole doesn't exists with start and end

 * address values.

 *

 * This mask is used to remove the upper 16bits of the VA and so come up with

 * the linear addr value.

 */

#define AMDGPU_GMC_HOLE_MASK	0x0000ffffffffffffULL



struct firmware;



/*
@@ -133,6 +146,19 @@ static inline bool amdgpu_gmc_vram_full_visible(struct amdgpu_gmc *gmc) 
	return (gmc->real_vram_size == gmc->visible_vram_size);

}



/**

 * amdgpu_gmc_sign_extend - sign extend the given gmc address

 *

 * @addr: address to extend

 */

static inline uint64_t amdgpu_gmc_sign_extend(uint64_t addr)

{

	if (addr >= AMDGPU_GMC_HOLE_START)

		addr |= AMDGPU_GMC_HOLE_END;



	return addr;

}



void amdgpu_gmc_get_pde_for_bo(struct amdgpu_bo *bo, int level,

			       uint64_t *addr, uint64_t *flags);

uint64_t amdgpu_gmc_pd_addr(struct amdgpu_bo *bo);

drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c

+4 −4
Original line number Diff line number Diff line
@@ -655,11 +655,11 @@ static int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file 


		dev_info.virtual_address_offset = AMDGPU_VA_RESERVED_SIZE;

		dev_info.virtual_address_max =

			min(vm_size, AMDGPU_VA_HOLE_START);

			min(vm_size, AMDGPU_GMC_HOLE_START);



		if (vm_size > AMDGPU_VA_HOLE_START) {

			dev_info.high_va_offset = AMDGPU_VA_HOLE_END;

			dev_info.high_va_max = AMDGPU_VA_HOLE_END | vm_size;

		if (vm_size > AMDGPU_GMC_HOLE_START) {

			dev_info.high_va_offset = AMDGPU_GMC_HOLE_END;

			dev_info.high_va_max = AMDGPU_GMC_HOLE_END | vm_size;

		}

		dev_info.virtual_address_alignment = max((int)PAGE_SIZE, AMDGPU_GPU_PAGE_SIZE);

		dev_info.pte_fragment_size = (1 << adev->vm_manager.fragment_size) * AMDGPU_GPU_PAGE_SIZE;

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