Commit ad98a18b authored by Benoit Cousson's avatar Benoit Cousson Committed by Paul Walmsley
Browse files

OMAP4: prcm: Fix errors in few defines name 



A couple of macros were wrongly changed during the _MOD to _INST
rename done in the following commit:

  OMAP4: PRCM: rename _MOD macros to _INST
  cdb54c44

Fix them to their original name.

Some CM and PRM instances were not well aligned. Align them.

Remove one blank line in cm2_44xx.h to align the output with
the other (cm1_44xx.h, prm44xx.h) files.

Update header copyright date.

Signed-off-by: default avatarBenoit Cousson <b-cousson@ti.com>
Cc: Paul Walmsley <paul@pwsan.com>
Cc: Rajendra Nayak <rnayak@ti.com>
Signed-off-by: default avatarPaul Walmsley <paul@pwsan.com>
parent ecba3287

arch/arm/mach-omap2/cm1_44xx.h

+14 −14
Original line number Diff line number Diff line 
/*

 * OMAP44xx CM1 instance offset macros

 *

 * Copyright (C) 2009-2010 Texas Instruments, Inc.

 * Copyright (C) 2009-2011 Texas Instruments, Inc.

 * Copyright (C) 2009-2010 Nokia Corporation

 *

 * Paul Walmsley (paul@pwsan.com)
@@ -41,9 +41,9 @@ 
#define OMAP4430_CM1_INSTR_INST		0x0f00



/* CM1 clockdomain register offsets (from instance start) */

#define OMAP4430_CM1_ABE_ABE_CDOFFS		0x0000

#define OMAP4430_CM1_MPU_MPU_CDOFFS	0x0000

#define OMAP4430_CM1_TESLA_TESLA_CDOFFS	0x0000

#define OMAP4430_CM1_ABE_ABE_CDOFFS	0x0000



/* CM1 */
@@ -82,8 +82,8 @@ 
#define OMAP4430_CM_DIV_M7_DPLL_CORE			OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0044)

#define OMAP4_CM_SSC_DELTAMSTEP_DPLL_CORE_OFFSET	0x0048

#define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_CORE		OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0048)

#define OMAP4_CM_SSC_INSTFREQDIV_DPLL_CORE_OFFSET	0x004c

#define OMAP4430_CM_SSC_INSTFREQDIV_DPLL_CORE		OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x004c)

#define OMAP4_CM_SSC_MODFREQDIV_DPLL_CORE_OFFSET	0x004c

#define OMAP4430_CM_SSC_MODFREQDIV_DPLL_CORE		OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x004c)

#define OMAP4_CM_EMU_OVERRIDE_DPLL_CORE_OFFSET		0x0050

#define OMAP4430_CM_EMU_OVERRIDE_DPLL_CORE		OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0050)

#define OMAP4_CM_CLKMODE_DPLL_MPU_OFFSET		0x0060
@@ -98,8 +98,8 @@ 
#define OMAP4430_CM_DIV_M2_DPLL_MPU			OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0070)

#define OMAP4_CM_SSC_DELTAMSTEP_DPLL_MPU_OFFSET		0x0088

#define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_MPU		OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0088)

#define OMAP4_CM_SSC_INSTFREQDIV_DPLL_MPU_OFFSET		0x008c

#define OMAP4430_CM_SSC_INSTFREQDIV_DPLL_MPU		OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x008c)

#define OMAP4_CM_SSC_MODFREQDIV_DPLL_MPU_OFFSET		0x008c

#define OMAP4430_CM_SSC_MODFREQDIV_DPLL_MPU		OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x008c)

#define OMAP4_CM_BYPCLK_DPLL_MPU_OFFSET			0x009c

#define OMAP4430_CM_BYPCLK_DPLL_MPU			OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x009c)

#define OMAP4_CM_CLKMODE_DPLL_IVA_OFFSET		0x00a0
@@ -116,8 +116,8 @@ 
#define OMAP4430_CM_DIV_M5_DPLL_IVA			OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00bc)

#define OMAP4_CM_SSC_DELTAMSTEP_DPLL_IVA_OFFSET		0x00c8

#define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_IVA		OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00c8)

#define OMAP4_CM_SSC_INSTFREQDIV_DPLL_IVA_OFFSET		0x00cc

#define OMAP4430_CM_SSC_INSTFREQDIV_DPLL_IVA		OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00cc)

#define OMAP4_CM_SSC_MODFREQDIV_DPLL_IVA_OFFSET		0x00cc

#define OMAP4430_CM_SSC_MODFREQDIV_DPLL_IVA		OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00cc)

#define OMAP4_CM_BYPCLK_DPLL_IVA_OFFSET			0x00dc

#define OMAP4430_CM_BYPCLK_DPLL_IVA			OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00dc)

#define OMAP4_CM_CLKMODE_DPLL_ABE_OFFSET		0x00e0
@@ -134,8 +134,8 @@ 
#define OMAP4430_CM_DIV_M3_DPLL_ABE			OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00f4)

#define OMAP4_CM_SSC_DELTAMSTEP_DPLL_ABE_OFFSET		0x0108

#define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_ABE		OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0108)

#define OMAP4_CM_SSC_INSTFREQDIV_DPLL_ABE_OFFSET		0x010c

#define OMAP4430_CM_SSC_INSTFREQDIV_DPLL_ABE		OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x010c)

#define OMAP4_CM_SSC_MODFREQDIV_DPLL_ABE_OFFSET		0x010c

#define OMAP4430_CM_SSC_MODFREQDIV_DPLL_ABE		OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x010c)

#define OMAP4_CM_CLKMODE_DPLL_DDRPHY_OFFSET		0x0120

#define OMAP4430_CM_CLKMODE_DPLL_DDRPHY			OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0120)

#define OMAP4_CM_IDLEST_DPLL_DDRPHY_OFFSET		0x0124
@@ -154,8 +154,8 @@ 
#define OMAP4430_CM_DIV_M6_DPLL_DDRPHY			OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0140)

#define OMAP4_CM_SSC_DELTAMSTEP_DPLL_DDRPHY_OFFSET	0x0148

#define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_DDRPHY		OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0148)

#define OMAP4_CM_SSC_INSTFREQDIV_DPLL_DDRPHY_OFFSET	0x014c

#define OMAP4430_CM_SSC_INSTFREQDIV_DPLL_DDRPHY		OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x014c)

#define OMAP4_CM_SSC_MODFREQDIV_DPLL_DDRPHY_OFFSET	0x014c

#define OMAP4430_CM_SSC_MODFREQDIV_DPLL_DDRPHY		OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x014c)

#define OMAP4_CM_SHADOW_FREQ_CONFIG1_OFFSET		0x0160

#define OMAP4430_CM_SHADOW_FREQ_CONFIG1			OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0160)

#define OMAP4_CM_SHADOW_FREQ_CONFIG2_OFFSET		0x0164

arch/arm/mach-omap2/cm2_44xx.h

+11 −12
Original line number Diff line number Diff line 
/*

 * OMAP44xx CM2 instance offset macros

 *

 * Copyright (C) 2009-2010 Texas Instruments, Inc.

 * Copyright (C) 2009-2011 Texas Instruments, Inc.

 * Copyright (C) 2009-2010 Nokia Corporation

 *

 * Paul Walmsley (paul@pwsan.com)
@@ -65,7 +65,6 @@ 
#define OMAP4430_CM2_L4PER_L4SEC_CDOFFS		0x0180

#define OMAP4430_CM2_CEFUSE_CEFUSE_CDOFFS	0x0000





/* CM2 */



/* CM2.OCP_SOCKET_CM2 register offsets */
@@ -121,8 +120,8 @@ 
#define OMAP4430_CM_DIV_M7_DPLL_PER			OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0064)

#define OMAP4_CM_SSC_DELTAMSTEP_DPLL_PER_OFFSET		0x0068

#define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_PER		OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0068)

#define OMAP4_CM_SSC_INSTFREQDIV_DPLL_PER_OFFSET		0x006c

#define OMAP4430_CM_SSC_INSTFREQDIV_DPLL_PER		OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x006c)

#define OMAP4_CM_SSC_MODFREQDIV_DPLL_PER_OFFSET		0x006c

#define OMAP4430_CM_SSC_MODFREQDIV_DPLL_PER		OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x006c)

#define OMAP4_CM_CLKMODE_DPLL_USB_OFFSET		0x0080

#define OMAP4430_CM_CLKMODE_DPLL_USB			OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0080)

#define OMAP4_CM_IDLEST_DPLL_USB_OFFSET			0x0084
@@ -135,8 +134,8 @@ 
#define OMAP4430_CM_DIV_M2_DPLL_USB			OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0090)

#define OMAP4_CM_SSC_DELTAMSTEP_DPLL_USB_OFFSET		0x00a8

#define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_USB		OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x00a8)

#define OMAP4_CM_SSC_INSTFREQDIV_DPLL_USB_OFFSET		0x00ac

#define OMAP4430_CM_SSC_INSTFREQDIV_DPLL_USB		OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x00ac)

#define OMAP4_CM_SSC_MODFREQDIV_DPLL_USB_OFFSET		0x00ac

#define OMAP4430_CM_SSC_MODFREQDIV_DPLL_USB		OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x00ac)

#define OMAP4_CM_CLKDCOLDO_DPLL_USB_OFFSET		0x00b4

#define OMAP4430_CM_CLKDCOLDO_DPLL_USB			OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x00b4)

#define OMAP4_CM_CLKMODE_DPLL_UNIPRO_OFFSET		0x00c0
@@ -151,8 +150,8 @@ 
#define OMAP4430_CM_DIV_M2_DPLL_UNIPRO			OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x00d0)

#define OMAP4_CM_SSC_DELTAMSTEP_DPLL_UNIPRO_OFFSET	0x00e8

#define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_UNIPRO		OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x00e8)

#define OMAP4_CM_SSC_INSTFREQDIV_DPLL_UNIPRO_OFFSET	0x00ec

#define OMAP4430_CM_SSC_INSTFREQDIV_DPLL_UNIPRO		OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x00ec)

#define OMAP4_CM_SSC_MODFREQDIV_DPLL_UNIPRO_OFFSET	0x00ec

#define OMAP4430_CM_SSC_MODFREQDIV_DPLL_UNIPRO		OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x00ec)



/* CM2.ALWAYS_ON_CM2 register offsets */

#define OMAP4_CM_ALWON_CLKSTCTRL_OFFSET			0x0000
@@ -227,8 +226,8 @@ 
#define OMAP4430_CM_D2D_DYNAMICDEP			OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0508)

#define OMAP4_CM_D2D_SAD2D_CLKCTRL_OFFSET		0x0520

#define OMAP4430_CM_D2D_SAD2D_CLKCTRL			OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0520)

#define OMAP4_CM_D2D_INSTEM_ICR_CLKCTRL_OFFSET		0x0528

#define OMAP4430_CM_D2D_INSTEM_ICR_CLKCTRL		OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0528)

#define OMAP4_CM_D2D_MODEM_ICR_CLKCTRL_OFFSET		0x0528

#define OMAP4430_CM_D2D_MODEM_ICR_CLKCTRL		OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0528)

#define OMAP4_CM_D2D_SAD2D_FW_CLKCTRL_OFFSET		0x0530

#define OMAP4430_CM_D2D_SAD2D_FW_CLKCTRL		OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0530)

#define OMAP4_CM_L4CFG_CLKSTCTRL_OFFSET			0x0600

arch/arm/mach-omap2/prm44xx.h

+11 −11
Original line number Diff line number Diff line
@@ -247,8 +247,8 @@ 
#define OMAP4430_RM_MEMIF_DLL_H_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x0464)

#define OMAP4_RM_D2D_SAD2D_CONTEXT_OFFSET		0x0524

#define OMAP4430_RM_D2D_SAD2D_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x0524)

#define OMAP4_RM_D2D_INSTEM_ICR_CONTEXT_OFFSET		0x052c

#define OMAP4430_RM_D2D_INSTEM_ICR_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x052c)

#define OMAP4_RM_D2D_MODEM_ICR_CONTEXT_OFFSET		0x052c

#define OMAP4430_RM_D2D_MODEM_ICR_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x052c)

#define OMAP4_RM_D2D_SAD2D_FW_CONTEXT_OFFSET		0x0534

#define OMAP4430_RM_D2D_SAD2D_FW_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x0534)

#define OMAP4_RM_L4CFG_L4_CFG_CONTEXT_OFFSET		0x0624
@@ -713,8 +713,8 @@ 
#define OMAP4430_PRM_VC_VAL_BYPASS			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00a0)

#define OMAP4_PRM_VC_CFG_CHANNEL_OFFSET			0x00a4

#define OMAP4430_PRM_VC_CFG_CHANNEL			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00a4)

#define OMAP4_PRM_VC_CFG_I2C_INSTE_OFFSET		0x00a8

#define OMAP4430_PRM_VC_CFG_I2C_INSTE			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00a8)

#define OMAP4_PRM_VC_CFG_I2C_MODE_OFFSET		0x00a8

#define OMAP4430_PRM_VC_CFG_I2C_MODE			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00a8)

#define OMAP4_PRM_VC_CFG_I2C_CLK_OFFSET			0x00ac

#define OMAP4430_PRM_VC_CFG_I2C_CLK			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00ac)

#define OMAP4_PRM_SRAM_COUNT_OFFSET			0x00b0
@@ -751,8 +751,8 @@ 
#define OMAP4430_PRM_PHASE2A_CNDP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00ec)

#define OMAP4_PRM_PHASE2B_CNDP_OFFSET			0x00f0

#define OMAP4430_PRM_PHASE2B_CNDP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00f0)

#define OMAP4_PRM_INSTEM_IF_CTRL_OFFSET			0x00f4

#define OMAP4430_PRM_INSTEM_IF_CTRL			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00f4)

#define OMAP4_PRM_MODEM_IF_CTRL_OFFSET			0x00f4

#define OMAP4430_PRM_MODEM_IF_CTRL			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00f4)

#define OMAP4_PRM_VC_ERRST_OFFSET			0x00f8

#define OMAP4430_PRM_VC_ERRST				OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00f8)

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