Commit ad756a16 authored by Mao, Junjie's avatar Mao, Junjie Committed by Avi Kivity
Browse files

KVM: VMX: Implement PCID/INVPCID for guests with EPT 



This patch handles PCID/INVPCID for guests.

Process-context identifiers (PCIDs) are a facility by which a logical processor
may cache information for multiple linear-address spaces so that the processor
may retain cached information when software switches to a different linear
address space. Refer to section 4.10.1 in IA32 Intel Software Developer's Manual
Volume 3A for details.

For guests with EPT, the PCID feature is enabled and INVPCID behaves as running
natively.
For guests without EPT, the PCID feature is disabled and INVPCID triggers #UD.

Signed-off-by: default avatarJunjie Mao <junjie.mao@intel.com>
Signed-off-by: default avatarAvi Kivity <avi@redhat.com>
parent fc73373b

arch/x86/include/asm/kvm_host.h

+3 −1
Original line number Diff line number Diff line
@@ -48,12 +48,13 @@ 


#define CR3_PAE_RESERVED_BITS ((X86_CR3_PWT | X86_CR3_PCD) - 1)

#define CR3_NONPAE_RESERVED_BITS ((PAGE_SIZE-1) & ~(X86_CR3_PWT | X86_CR3_PCD))

#define CR3_PCID_ENABLED_RESERVED_BITS 0xFFFFFF0000000000ULL

#define CR3_L_MODE_RESERVED_BITS (CR3_NONPAE_RESERVED_BITS |	\

				  0xFFFFFF0000000000ULL)

#define CR4_RESERVED_BITS                                               \

	(~(unsigned long)(X86_CR4_VME | X86_CR4_PVI | X86_CR4_TSD | X86_CR4_DE\

			  | X86_CR4_PSE | X86_CR4_PAE | X86_CR4_MCE     \

			  | X86_CR4_PGE | X86_CR4_PCE | X86_CR4_OSFXSR  \

			  | X86_CR4_PGE | X86_CR4_PCE | X86_CR4_OSFXSR | X86_CR4_PCIDE \

			  | X86_CR4_OSXSAVE | X86_CR4_SMEP | X86_CR4_RDWRGSFS \

			  | X86_CR4_OSXMMEXCPT | X86_CR4_VMXE))
@@ -673,6 +674,7 @@ struct kvm_x86_ops { 
	u64 (*get_mt_mask)(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio);

	int (*get_lpage_level)(void);

	bool (*rdtscp_supported)(void);

	bool (*invpcid_supported)(void);

	void (*adjust_tsc_offset)(struct kvm_vcpu *vcpu, s64 adjustment, bool host);



	void (*set_tdp_cr3)(struct kvm_vcpu *vcpu, unsigned long cr3);

arch/x86/include/asm/processor-flags.h

+2 −0
Original line number Diff line number Diff line
@@ -44,6 +44,7 @@ 
 */

#define X86_CR3_PWT	0x00000008 /* Page Write Through */

#define X86_CR3_PCD	0x00000010 /* Page Cache Disable */

#define X86_CR3_PCID_MASK 0x00000fff /* PCID Mask */



/*

 * Intel CPU features in CR4
@@ -61,6 +62,7 @@ 
#define X86_CR4_OSXMMEXCPT 0x00000400 /* enable unmasked SSE exceptions */

#define X86_CR4_VMXE	0x00002000 /* enable VMX virtualization */

#define X86_CR4_RDWRGSFS 0x00010000 /* enable RDWRGSFS support */

#define X86_CR4_PCIDE	0x00020000 /* enable PCID support */

#define X86_CR4_OSXSAVE 0x00040000 /* enable xsave and xrestore */

#define X86_CR4_SMEP	0x00100000 /* enable SMEP support */

arch/x86/include/asm/vmx.h

+2 −0
Original line number Diff line number Diff line
@@ -60,6 +60,7 @@ 
#define SECONDARY_EXEC_WBINVD_EXITING		0x00000040

#define SECONDARY_EXEC_UNRESTRICTED_GUEST	0x00000080

#define SECONDARY_EXEC_PAUSE_LOOP_EXITING	0x00000400

#define SECONDARY_EXEC_ENABLE_INVPCID		0x00001000





#define PIN_BASED_EXT_INTR_MASK                 0x00000001
@@ -281,6 +282,7 @@ enum vmcs_field { 
#define EXIT_REASON_EPT_MISCONFIG       49

#define EXIT_REASON_WBINVD		54

#define EXIT_REASON_XSETBV		55

#define EXIT_REASON_INVPCID		58



/*

 * Interruption-information format

arch/x86/kvm/cpuid.c

+3 −2
Original line number Diff line number Diff line
@@ -201,6 +201,7 @@ static int do_cpuid_ent(struct kvm_cpuid_entry2 *entry, u32 function, 
	unsigned f_lm = 0;

#endif

	unsigned f_rdtscp = kvm_x86_ops->rdtscp_supported() ? F(RDTSCP) : 0;

	unsigned f_invpcid = kvm_x86_ops->invpcid_supported() ? F(INVPCID) : 0;



	/* cpuid 1.edx */

	const u32 kvm_supported_word0_x86_features =
@@ -228,7 +229,7 @@ static int do_cpuid_ent(struct kvm_cpuid_entry2 *entry, u32 function, 
		0 /* DS-CPL, VMX, SMX, EST */ |

		0 /* TM2 */ | F(SSSE3) | 0 /* CNXT-ID */ | 0 /* Reserved */ |

		F(FMA) | F(CX16) | 0 /* xTPR Update, PDCM */ |

		0 /* Reserved, DCA */ | F(XMM4_1) |

		F(PCID) | 0 /* Reserved, DCA */ | F(XMM4_1) |

		F(XMM4_2) | F(X2APIC) | F(MOVBE) | F(POPCNT) |

		0 /* Reserved*/ | F(AES) | F(XSAVE) | 0 /* OSXSAVE */ | F(AVX) |

		F(F16C) | F(RDRAND);
@@ -248,7 +249,7 @@ static int do_cpuid_ent(struct kvm_cpuid_entry2 *entry, u32 function, 
	/* cpuid 7.0.ebx */

	const u32 kvm_supported_word9_x86_features =

		F(FSGSBASE) | F(BMI1) | F(HLE) | F(AVX2) | F(SMEP) |

		F(BMI2) | F(ERMS) | F(RTM);

		F(BMI2) | F(ERMS) | f_invpcid | F(RTM);



	/* all calls to cpuid_count() should be made on the same cpu */

	get_cpu();

arch/x86/kvm/cpuid.h

+8 −0
Original line number Diff line number Diff line
@@ -52,4 +52,12 @@ static inline bool guest_cpuid_has_osvw(struct kvm_vcpu *vcpu) 
	return best && (best->ecx & bit(X86_FEATURE_OSVW));

}



static inline bool guest_cpuid_has_pcid(struct kvm_vcpu *vcpu)

{

	struct kvm_cpuid_entry2 *best;



	best = kvm_find_cpuid_entry(vcpu, 1, 0);

	return best && (best->ecx & bit(X86_FEATURE_PCID));

}



#endif

CRA Git | Maintained and supported by SUSTech CRA and CCSE