clk: meson-g12a: add temperature sensor clocks (ad517d52) · Commits · 戴 / test

drivers/clk/meson/g12a.c

+31 −0

Original line number	Diff line number	Diff line
		@@ -2504,6 +2504,33 @@ static struct clk_regmap g12a_mali = {
		},
		};

		static struct clk_regmap g12a_ts_div = {
		.data = &(struct clk_regmap_div_data){
		.offset = HHI_TS_CLK_CNTL,
		.shift = 0,
		.width = 8,
		},
		.hw.init = &(struct clk_init_data){
		.name = "ts_div",
		.ops = &clk_regmap_divider_ro_ops,
		.parent_names = (const char *[]){ "xtal" },
		.num_parents = 1,
		},
		};

		static struct clk_regmap g12a_ts = {
		.data = &(struct clk_regmap_gate_data){
		.offset = HHI_TS_CLK_CNTL,
		.bit_idx = 8,
		},
		.hw.init = &(struct clk_init_data){
		.name = "ts",
		.ops = &clk_regmap_gate_ops,
		.parent_names = (const char *[]){ "ts_div" },
		.num_parents = 1,
		},
		};

		/* Everything Else (EE) domain gates */
		static MESON_GATE(g12a_ddr, HHI_GCLK_MPEG0, 0);
		static MESON_GATE(g12a_dos, HHI_GCLK_MPEG0, 1);
		@@ -2793,6 +2820,8 @@ static struct clk_hw_onecell_data g12a_hw_onecell_data = {
		[CLKID_VDEC_HEVCF_SEL] = &g12a_vdec_hevcf_sel.hw,
		[CLKID_VDEC_HEVCF_DIV] = &g12a_vdec_hevcf_div.hw,
		[CLKID_VDEC_HEVCF] = &g12a_vdec_hevcf.hw,
		[CLKID_TS_DIV] = &g12a_ts_div.hw,
		[CLKID_TS] = &g12a_ts.hw,
		[NR_CLKS] = NULL,
		},
		.num = NR_CLKS,
		@@ -2990,6 +3019,8 @@ static struct clk_regmap *const g12a_clk_regmaps[] = {
		&g12a_vdec_hevcf_sel,
		&g12a_vdec_hevcf_div,
		&g12a_vdec_hevcf,
		&g12a_ts_div,
		&g12a_ts,
		};

		static const struct reg_sequence g12a_init_regs[] = {

+2 −1

Original line number	Diff line number	Diff line
		@@ -195,8 +195,9 @@
		#define CLKID_VDEC_HEVC_DIV 206
		#define CLKID_VDEC_HEVCF_SEL 208
		#define CLKID_VDEC_HEVCF_DIV 209
		#define CLKID_TS_DIV 211

		#define NR_CLKS 211
		#define NR_CLKS 213

		/* include the CLKIDs that have been made part of the DT binding */
		#include <dt-bindings/clock/g12a-clkc.h>