Commit ad40f8b3 authored by Ville Syrjälä's avatar Ville Syrjälä
Browse files

drm/i915: Nuke icl_calc_dp_combo_pll_link() 



We already have the code to calculate the WRPLL output clock from
the register values, but for some reason we're only using it for
HDMI and not DP. Throw out the inflexible DP DPLL table lookup and
just call the HDMI code which decodes the actual register values.

Signed-off-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20190207173230.22368-12-ville.syrjala@linux.intel.com


Reviewed-by: default avatarLucas De Marchi <lucas.demarchi@intel.com>
parent 2ee7fd1e

drivers/gpu/drm/i915/intel_ddi.c

+1 −5
Original line number Diff line number Diff line
@@ -1477,11 +1477,7 @@ static void icl_ddi_clock_get(struct intel_encoder *encoder, 


	pll_id = intel_get_shared_dpll_id(dev_priv, pipe_config->shared_dpll);

	if (intel_port_is_combophy(dev_priv, port)) {

		if (intel_crtc_has_type(pipe_config, INTEL_OUTPUT_HDMI))

		link_clock = cnl_calc_wrpll_link(dev_priv, pll_id);

		else

			link_clock = icl_calc_dp_combo_pll_link(dev_priv,

								pll_id);

	} else {

		if (pll_id == DPLL_ID_ICL_TBTPLL)

			link_clock = icl_calc_tbt_pll_link(dev_priv, port);

drivers/gpu/drm/i915/intel_dpll_mgr.c

+0 −70
Original line number Diff line number Diff line
@@ -2561,76 +2561,6 @@ static bool icl_calc_dpll_state(struct intel_crtc_state *crtc_state, 
	return true;

}



int icl_calc_dp_combo_pll_link(struct drm_i915_private *dev_priv,

			       u32 pll_id)

{

	u32 cfgcr0, cfgcr1;

	u32 pdiv, kdiv, qdiv_mode, qdiv_ratio, dco_integer, dco_fraction;

	const struct skl_wrpll_params *params;

	int index, n_entries, link_clock;



	/* Read back values from DPLL CFGCR registers */

	cfgcr0 = I915_READ(ICL_DPLL_CFGCR0(pll_id));

	cfgcr1 = I915_READ(ICL_DPLL_CFGCR1(pll_id));



	dco_integer = cfgcr0 & DPLL_CFGCR0_DCO_INTEGER_MASK;

	dco_fraction = (cfgcr0 & DPLL_CFGCR0_DCO_FRACTION_MASK) >>

		DPLL_CFGCR0_DCO_FRACTION_SHIFT;

	pdiv = (cfgcr1 & DPLL_CFGCR1_PDIV_MASK) >> DPLL_CFGCR1_PDIV_SHIFT;

	kdiv = (cfgcr1 & DPLL_CFGCR1_KDIV_MASK) >> DPLL_CFGCR1_KDIV_SHIFT;

	qdiv_mode = (cfgcr1 & DPLL_CFGCR1_QDIV_MODE(1)) >>

		DPLL_CFGCR1_QDIV_MODE_SHIFT;

	qdiv_ratio = (cfgcr1 & DPLL_CFGCR1_QDIV_RATIO_MASK) >>

		DPLL_CFGCR1_QDIV_RATIO_SHIFT;



	params = dev_priv->cdclk.hw.ref == 24000 ?

		icl_dp_combo_pll_24MHz_values :

		icl_dp_combo_pll_19_2MHz_values;

	n_entries = ARRAY_SIZE(icl_dp_combo_pll_24MHz_values);



	for (index = 0; index < n_entries; index++) {

		if (dco_integer == params[index].dco_integer &&

		    dco_fraction == params[index].dco_fraction &&

		    pdiv == params[index].pdiv &&

		    kdiv == params[index].kdiv &&

		    qdiv_mode == params[index].qdiv_mode &&

		    qdiv_ratio == params[index].qdiv_ratio)

			break;

	}



	/* Map PLL Index to Link Clock */

	switch (index) {

	default:

		MISSING_CASE(index);

		/* fall through */

	case 0:

		link_clock = 540000;

		break;

	case 1:

		link_clock = 270000;

		break;

	case 2:

		link_clock = 162000;

		break;

	case 3:

		link_clock = 324000;

		break;

	case 4:

		link_clock = 216000;

		break;

	case 5:

		link_clock = 432000;

		break;

	case 6:

		link_clock = 648000;

		break;

	case 7:

		link_clock = 810000;

		break;

	}



	return link_clock;

}



static enum tc_port icl_pll_id_to_tc_port(enum intel_dpll_id id)

{

drivers/gpu/drm/i915/intel_dpll_mgr.h

+0 −2
Original line number Diff line number Diff line
@@ -340,8 +340,6 @@ void intel_shared_dpll_init(struct drm_device *dev); 


void intel_dpll_dump_hw_state(struct drm_i915_private *dev_priv,

			      struct intel_dpll_hw_state *hw_state);

int icl_calc_dp_combo_pll_link(struct drm_i915_private *dev_priv,

			       u32 pll_id);

int cnl_hdmi_pll_ref_clock(struct drm_i915_private *dev_priv);

enum intel_dpll_id icl_tc_port_to_pll_id(enum tc_port tc_port);

bool intel_dpll_is_combophy(enum intel_dpll_id id);

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