drm/i915: Enforce max hdisplay/hblank_start limits on HSW/BDW FDI (ad193bc6) · Commits · 戴 / test

The PCH transcoder registers are only 12 bits wide for the hdisplay and hblank_start values. On HSW/BDW the CPU side registers are 13 bits wide. intel_mode_valid() only checks against the higher limit (since we don't know where the mode is to be used), so an extra check is required against the FDI limits. Signed-off-by:

Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20180615174406.12258-3-ville.syrjala@linux.intel.com Reviewed-by:

Paulo Zanoni <paulo.r.zanoni@intel.com>

drivers/gpu/drm/i915/intel_crt.c

+9 −0

Original line number	Diff line number	Diff line
		@@ -337,6 +337,10 @@ intel_crt_mode_valid(struct drm_connector *connector,
		(ironlake_get_lanes_required(mode->clock, 270000, 24) > 2))
		return MODE_CLOCK_HIGH;

		/* HSW/BDW FDI limited to 4k */
		if (mode->hdisplay > 4096)
		return MODE_H_ILLEGAL;

		return MODE_OK;
		}

		@@ -379,6 +383,11 @@ static bool hsw_crt_compute_config(struct intel_encoder *encoder,
		if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
		return false;

		/* HSW/BDW FDI limited to 4k */
		if (adjusted_mode->crtc_hdisplay > 4096 \|\|
		adjusted_mode->crtc_hblank_start > 4096)
		return false;

		pipe_config->has_pch_encoder = true;

		/* LPT FDI RX only supports 8bpc. */

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