Commit acfdc56d authored by Jongpill Lee's avatar Jongpill Lee Committed by Kukjin Kim
Browse files

ARM: S5PV310: Add serial port support 



This patch adds UART serial port support for S5PV310.
In the case of that serial device has just one clock source, driver can not
control clock source. So add check function in get_clksrc and set_clksrc.

Signed-off-by: default avatarJongpill Lee <boyko.lee@samsung.com>
Acked-by: default avatarChanghwan Youn <chaos.youn@samsung.com>
Signed-off-by: default avatarKukjin Kim <kgene.kim@samsung.com>
parent b1d69cc6

drivers/serial/Kconfig

+2 −2
Original line number Diff line number Diff line
@@ -544,8 +544,8 @@ config SERIAL_S3C6400 


config SERIAL_S5PV210

	tristate "Samsung S5PV210 Serial port support"

	depends on SERIAL_SAMSUNG && (CPU_S5PV210 || CPU_S5P6442)

	select SERIAL_SAMSUNG_UARTS_4 if CPU_S5PV210

	depends on SERIAL_SAMSUNG && (CPU_S5PV210 || CPU_S5P6442 || CPU_S5PV310)

	select SERIAL_SAMSUNG_UARTS_4 if (CPU_S5PV210 || CPU_S5PV310)

	default y

	help

	  Serial port support for Samsung's S5P Family of SoC's

drivers/serial/s5pv210.c

+8 −0
Original line number Diff line number Diff line
@@ -28,8 +28,12 @@ 
static int s5pv210_serial_setsource(struct uart_port *port,

					struct s3c24xx_uart_clksrc *clk)

{

	struct s3c2410_uartcfg *cfg = port->dev->platform_data;

	unsigned long ucon = rd_regl(port, S3C2410_UCON);



	if ((cfg->clocks_size) == 1)

		return 0;



	if (strcmp(clk->name, "pclk") == 0)

		ucon &= ~S5PV210_UCON_CLKMASK;

	else if (strcmp(clk->name, "uclk1") == 0)
@@ -47,10 +51,14 @@ static int s5pv210_serial_setsource(struct uart_port *port, 
static int s5pv210_serial_getsource(struct uart_port *port,

					struct s3c24xx_uart_clksrc *clk)

{

	struct s3c2410_uartcfg *cfg = port->dev->platform_data;

	u32 ucon = rd_regl(port, S3C2410_UCON);



	clk->divisor = 1;



	if ((cfg->clocks_size) == 1)

		return 0;



	switch (ucon & S5PV210_UCON_CLKMASK) {

	case S5PV210_UCON_PCLK:

		clk->name = "pclk";

CRA Git | Maintained and supported by SUSTech CRA and CCSE