Commit acddfc2c authored by Weiyi Lu's avatar Weiyi Lu Committed by Stephen Boyd
Browse files

clk: mediatek: Add MT8183 clock support 



Add MT8183 clock support, include topckgen, apmixedsys,
infracfg, mcucfg and subsystem clocks.

Signed-off-by: default avatarWeiyi Lu <weiyi.lu@mediatek.com>
Tested-by: default avatarNicolas Boichat <drinkcat@chromium.org>
Reviewed-by: default avatarNicolas Boichat <drinkcat@chromium.org>
Signed-off-by: default avatarStephen Boyd <sboyd@kernel.org>
parent 23fe31de

drivers/clk/mediatek/Kconfig

+75 −0
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@@ -216,4 +216,79 @@ config COMMON_CLK_MT8173 
	default ARCH_MEDIATEK

	default ARCH_MEDIATEK

	---help---

	---help---

	  This driver supports MediaTek MT8173 clocks.

	  This driver supports MediaTek MT8173 clocks.



config COMMON_CLK_MT8183

	bool "Clock driver for MediaTek MT8183"

	depends on (ARCH_MEDIATEK && ARM64) || COMPILE_TEST

	select COMMON_CLK_MEDIATEK

	default ARCH_MEDIATEK && ARM64

	help

	  This driver supports MediaTek MT8183 basic clocks.



config COMMON_CLK_MT8183_AUDIOSYS

	bool "Clock driver for MediaTek MT8183 audiosys"

	depends on COMMON_CLK_MT8183

	help

	  This driver supports MediaTek MT8183 audiosys clocks.



config COMMON_CLK_MT8183_CAMSYS

	bool "Clock driver for MediaTek MT8183 camsys"

	depends on COMMON_CLK_MT8183

	help

	  This driver supports MediaTek MT8183 camsys clocks.



config COMMON_CLK_MT8183_IMGSYS

	bool "Clock driver for MediaTek MT8183 imgsys"

	depends on COMMON_CLK_MT8183

	help

	  This driver supports MediaTek MT8183 imgsys clocks.



config COMMON_CLK_MT8183_IPU_CORE0

	bool "Clock driver for MediaTek MT8183 ipu_core0"

	depends on COMMON_CLK_MT8183

	help

	  This driver supports MediaTek MT8183 ipu_core0 clocks.



config COMMON_CLK_MT8183_IPU_CORE1

	bool "Clock driver for MediaTek MT8183 ipu_core1"

	depends on COMMON_CLK_MT8183

	help

	  This driver supports MediaTek MT8183 ipu_core1 clocks.



config COMMON_CLK_MT8183_IPU_ADL

	bool "Clock driver for MediaTek MT8183 ipu_adl"

	depends on COMMON_CLK_MT8183

	help

	  This driver supports MediaTek MT8183 ipu_adl clocks.



config COMMON_CLK_MT8183_IPU_CONN

	bool "Clock driver for MediaTek MT8183 ipu_conn"

	depends on COMMON_CLK_MT8183

	help

	  This driver supports MediaTek MT8183 ipu_conn clocks.



config COMMON_CLK_MT8183_MFGCFG

	bool "Clock driver for MediaTek MT8183 mfgcfg"

	depends on COMMON_CLK_MT8183

	help

	  This driver supports MediaTek MT8183 mfgcfg clocks.



config COMMON_CLK_MT8183_MMSYS

	bool "Clock driver for MediaTek MT8183 mmsys"

	depends on COMMON_CLK_MT8183

	help

	  This driver supports MediaTek MT8183 mmsys clocks.



config COMMON_CLK_MT8183_VDECSYS

	bool "Clock driver for MediaTek MT8183 vdecsys"

	depends on COMMON_CLK_MT8183

	help

	  This driver supports MediaTek MT8183 vdecsys clocks.



config COMMON_CLK_MT8183_VENCSYS

	bool "Clock driver for MediaTek MT8183 vencsys"

	depends on COMMON_CLK_MT8183

	help

	  This driver supports MediaTek MT8183 vencsys clocks.



endmenu
 
endmenu

drivers/clk/mediatek/Makefile

+12 −0
Original line number Original line Diff line number Diff line
@@ -32,3 +32,15 @@ obj-$(CONFIG_COMMON_CLK_MT7629_ETHSYS) += clk-mt7629-eth.o 
obj-$(CONFIG_COMMON_CLK_MT7629_HIFSYS) += clk-mt7629-hif.o

obj-$(CONFIG_COMMON_CLK_MT7629_HIFSYS) += clk-mt7629-hif.o

obj-$(CONFIG_COMMON_CLK_MT8135) += clk-mt8135.o

obj-$(CONFIG_COMMON_CLK_MT8135) += clk-mt8135.o

obj-$(CONFIG_COMMON_CLK_MT8173) += clk-mt8173.o

obj-$(CONFIG_COMMON_CLK_MT8173) += clk-mt8173.o

obj-$(CONFIG_COMMON_CLK_MT8183) += clk-mt8183.o

obj-$(CONFIG_COMMON_CLK_MT8183_AUDIOSYS) += clk-mt8183-audio.o

obj-$(CONFIG_COMMON_CLK_MT8183_CAMSYS) += clk-mt8183-cam.o

obj-$(CONFIG_COMMON_CLK_MT8183_IMGSYS) += clk-mt8183-img.o

obj-$(CONFIG_COMMON_CLK_MT8183_IPU_CORE0) += clk-mt8183-ipu0.o

obj-$(CONFIG_COMMON_CLK_MT8183_IPU_CORE1) += clk-mt8183-ipu1.o

obj-$(CONFIG_COMMON_CLK_MT8183_IPU_ADL) += clk-mt8183-ipu_adl.o

obj-$(CONFIG_COMMON_CLK_MT8183_IPU_CONN) += clk-mt8183-ipu_conn.o

obj-$(CONFIG_COMMON_CLK_MT8183_MFGCFG) += clk-mt8183-mfgcfg.o

obj-$(CONFIG_COMMON_CLK_MT8183_MMSYS) += clk-mt8183-mm.o

obj-$(CONFIG_COMMON_CLK_MT8183_VDECSYS) += clk-mt8183-vdec.o

obj-$(CONFIG_COMMON_CLK_MT8183_VENCSYS) += clk-mt8183-venc.o

drivers/clk/mediatek/clk-gate.h

+14 −0
Original line number Original line Diff line number Diff line
@@ -50,4 +50,18 @@ struct clk *mtk_clk_register_gate( 
		const struct clk_ops *ops,

		const struct clk_ops *ops,

		unsigned long flags);

		unsigned long flags);





#define GATE_MTK_FLAGS(_id, _name, _parent, _regs, _shift,	\

			_ops, _flags) {				\

		.id = _id,					\

		.name = _name,					\

		.parent_name = _parent,				\

		.regs = _regs,					\

		.shift = _shift,				\

		.ops = _ops,					\

		.flags = _flags,				\

	}



#define GATE_MTK(_id, _name, _parent, _regs, _shift, _ops)		\

	GATE_MTK_FLAGS(_id, _name, _parent, _regs, _shift, _ops, 0)



#endif /* __DRV_CLK_GATE_H */
 
#endif /* __DRV_CLK_GATE_H */

drivers/clk/mediatek/clk-mt8183-audio.c

0 → 100644
+105 −0
Original line number Original line Diff line number Diff line 
// SPDX-License-Identifier: GPL-2.0

//

// Copyright (c) 2018 MediaTek Inc.

// Author: Weiyi Lu <weiyi.lu@mediatek.com>



#include <linux/clk-provider.h>

#include <linux/of_platform.h>

#include <linux/platform_device.h>



#include "clk-mtk.h"

#include "clk-gate.h"



#include <dt-bindings/clock/mt8183-clk.h>



static const struct mtk_gate_regs audio0_cg_regs = {

	.set_ofs = 0x0,

	.clr_ofs = 0x0,

	.sta_ofs = 0x0,

};



static const struct mtk_gate_regs audio1_cg_regs = {

	.set_ofs = 0x4,

	.clr_ofs = 0x4,

	.sta_ofs = 0x4,

};



#define GATE_AUDIO0(_id, _name, _parent, _shift)		\

	GATE_MTK(_id, _name, _parent, &audio0_cg_regs, _shift,	\

		&mtk_clk_gate_ops_no_setclr)



#define GATE_AUDIO1(_id, _name, _parent, _shift)		\

	GATE_MTK(_id, _name, _parent, &audio1_cg_regs, _shift,	\

		&mtk_clk_gate_ops_no_setclr)



static const struct mtk_gate audio_clks[] = {

	/* AUDIO0 */

	GATE_AUDIO0(CLK_AUDIO_AFE, "aud_afe", "audio_sel",

		2),

	GATE_AUDIO0(CLK_AUDIO_22M, "aud_22m", "aud_eng1_sel",

		8),

	GATE_AUDIO0(CLK_AUDIO_24M, "aud_24m", "aud_eng2_sel",

		9),

	GATE_AUDIO0(CLK_AUDIO_APLL2_TUNER, "aud_apll2_tuner", "aud_eng2_sel",

		18),

	GATE_AUDIO0(CLK_AUDIO_APLL_TUNER, "aud_apll_tuner", "aud_eng1_sel",

		19),

	GATE_AUDIO0(CLK_AUDIO_TDM, "aud_tdm", "apll12_divb",

		20),

	GATE_AUDIO0(CLK_AUDIO_ADC, "aud_adc", "audio_sel",

		24),

	GATE_AUDIO0(CLK_AUDIO_DAC, "aud_dac", "audio_sel",

		25),

	GATE_AUDIO0(CLK_AUDIO_DAC_PREDIS, "aud_dac_predis", "audio_sel",

		26),

	GATE_AUDIO0(CLK_AUDIO_TML, "aud_tml", "audio_sel",

		27),

	/* AUDIO1 */

	GATE_AUDIO1(CLK_AUDIO_I2S1, "aud_i2s1", "audio_sel",

		4),

	GATE_AUDIO1(CLK_AUDIO_I2S2, "aud_i2s2", "audio_sel",

		5),

	GATE_AUDIO1(CLK_AUDIO_I2S3, "aud_i2s3", "audio_sel",

		6),

	GATE_AUDIO1(CLK_AUDIO_I2S4, "aud_i2s4", "audio_sel",

		7),

	GATE_AUDIO1(CLK_AUDIO_PDN_ADDA6_ADC, "aud_pdn_adda6_adc", "audio_sel",

		20),

};



static int clk_mt8183_audio_probe(struct platform_device *pdev)

{

	struct clk_onecell_data *clk_data;

	int r;

	struct device_node *node = pdev->dev.of_node;



	clk_data = mtk_alloc_clk_data(CLK_AUDIO_NR_CLK);



	mtk_clk_register_gates(node, audio_clks, ARRAY_SIZE(audio_clks),

			clk_data);



	r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);

	if (r)

		return r;



	r = devm_of_platform_populate(&pdev->dev);

	if (r)

		of_clk_del_provider(node);



	return r;

}



static const struct of_device_id of_match_clk_mt8183_audio[] = {

	{ .compatible = "mediatek,mt8183-audiosys", },

	{}

};



static struct platform_driver clk_mt8183_audio_drv = {

	.probe = clk_mt8183_audio_probe,

	.driver = {

		.name = "clk-mt8183-audio",

		.of_match_table = of_match_clk_mt8183_audio,

	},

};



builtin_platform_driver(clk_mt8183_audio_drv);

drivers/clk/mediatek/clk-mt8183-cam.c

0 → 100644
+63 −0
Original line number Original line Diff line number Diff line 
// SPDX-License-Identifier: GPL-2.0

//

// Copyright (c) 2018 MediaTek Inc.

// Author: Weiyi Lu <weiyi.lu@mediatek.com>



#include <linux/clk-provider.h>

#include <linux/platform_device.h>



#include "clk-mtk.h"

#include "clk-gate.h"



#include <dt-bindings/clock/mt8183-clk.h>



static const struct mtk_gate_regs cam_cg_regs = {

	.set_ofs = 0x4,

	.clr_ofs = 0x8,

	.sta_ofs = 0x0,

};



#define GATE_CAM(_id, _name, _parent, _shift)			\

	GATE_MTK(_id, _name, _parent, &cam_cg_regs, _shift,	\

		&mtk_clk_gate_ops_setclr)



static const struct mtk_gate cam_clks[] = {

	GATE_CAM(CLK_CAM_LARB6, "cam_larb6", "cam_sel", 0),

	GATE_CAM(CLK_CAM_DFP_VAD, "cam_dfp_vad", "cam_sel", 1),

	GATE_CAM(CLK_CAM_LARB3, "cam_larb3", "cam_sel", 2),

	GATE_CAM(CLK_CAM_CAM, "cam_cam", "cam_sel", 6),

	GATE_CAM(CLK_CAM_CAMTG, "cam_camtg", "cam_sel", 7),

	GATE_CAM(CLK_CAM_SENINF, "cam_seninf", "cam_sel", 8),

	GATE_CAM(CLK_CAM_CAMSV0, "cam_camsv0", "cam_sel", 9),

	GATE_CAM(CLK_CAM_CAMSV1, "cam_camsv1", "cam_sel", 10),

	GATE_CAM(CLK_CAM_CAMSV2, "cam_camsv2", "cam_sel", 11),

	GATE_CAM(CLK_CAM_CCU, "cam_ccu", "cam_sel", 12),

};



static int clk_mt8183_cam_probe(struct platform_device *pdev)

{

	struct clk_onecell_data *clk_data;

	struct device_node *node = pdev->dev.of_node;



	clk_data = mtk_alloc_clk_data(CLK_CAM_NR_CLK);



	mtk_clk_register_gates(node, cam_clks, ARRAY_SIZE(cam_clks),

			clk_data);



	return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);

}



static const struct of_device_id of_match_clk_mt8183_cam[] = {

	{ .compatible = "mediatek,mt8183-camsys", },

	{}

};



static struct platform_driver clk_mt8183_cam_drv = {

	.probe = clk_mt8183_cam_probe,

	.driver = {

		.name = "clk-mt8183-cam",

		.of_match_table = of_match_clk_mt8183_cam,

	},

};



builtin_platform_driver(clk_mt8183_cam_drv);

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