Commit accc1ce7 authored by David Wu's avatar David Wu Committed by Linus Walleij
Browse files

pinctrl: rockchip: Add iomux-route switching support for rk3399 



There are 2 IP blocks pin routes need to be switched, that are
uart2dbg, pcie_clkreq.

Signed-off-by: default avatarDavid Wu <david.wu@rock-chips.com>
Reviewed-by: default avatarHeiko Stuebner <heiko@sntech.de>
Signed-off-by: default avatarLinus Walleij <linus.walleij@linaro.org>
parent cedc964a

drivers/pinctrl/pinctrl-rockchip.c

+41 −0
Original line number Diff line number Diff line
@@ -816,6 +816,45 @@ static struct rockchip_mux_route_data rk3328_mux_route_data[] = { 
	},

};



static struct rockchip_mux_route_data rk3399_mux_route_data[] = {

	{

		/* uart2dbga_rx */

		.bank_num = 4,

		.pin = 8,

		.func = 2,

		.route_offset = 0xe21c,

		.route_val = BIT(16 + 10) | BIT(16 + 11),

	}, {

		/* uart2dbgb_rx */

		.bank_num = 4,

		.pin = 16,

		.func = 2,

		.route_offset = 0xe21c,

		.route_val = BIT(16 + 10) | BIT(16 + 11) | BIT(10),

	}, {

		/* uart2dbgc_rx */

		.bank_num = 4,

		.pin = 19,

		.func = 1,

		.route_offset = 0xe21c,

		.route_val = BIT(16 + 10) | BIT(16 + 11) | BIT(11),

	}, {

		/* pcie_clkreqn */

		.bank_num = 2,

		.pin = 26,

		.func = 2,

		.route_offset = 0xe21c,

		.route_val = BIT(16 + 14),

	}, {

		/* pcie_clkreqnb */

		.bank_num = 4,

		.pin = 24,

		.func = 1,

		.route_offset = 0xe21c,

		.route_val = BIT(16 + 14) | BIT(14),

	},

};



static bool rockchip_get_mux_route(struct rockchip_pin_bank *bank, int pin,

				   int mux, u32 *reg, u32 *value)

{
@@ -3270,6 +3309,8 @@ static struct rockchip_pin_ctrl rk3399_pin_ctrl = { 
		.pmu_mux_offset		= 0x0,

		.grf_drv_offset		= 0xe100,

		.pmu_drv_offset		= 0x80,

		.iomux_routes		= rk3399_mux_route_data,

		.niomux_routes		= ARRAY_SIZE(rk3399_mux_route_data),

		.pull_calc_reg		= rk3399_calc_pull_reg_and_bit,

		.drv_calc_reg		= rk3399_calc_drv_reg_and_bit,

};

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