Commit acc4f98d authored by Anson Huang's avatar Anson Huang Committed by Stephen Boyd
Browse files

clk: imx6ul: add mmdc1 ipg clock



i.MX6UL has MMDC1 ipg clock in CCM CCGR, add it into
clock tree for clock management.

Signed-off-by: default avatarAnson Huang <Anson.Huang@nxp.com>
Reviewed-by: default avatarRob Herring <robh@kernel.org>
Signed-off-by: default avatarStephen Boyd <sboyd@kernel.org>
parent 5b394b2d
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+1 −0
Original line number Diff line number Diff line
@@ -408,6 +408,7 @@ static void __init imx6ul_clocks_init(struct device_node *ccm_node)
	clks[IMX6UL_CLK_WDOG1]		= imx_clk_gate2("wdog1",	"ipg",		base + 0x74,	16);
	clks[IMX6UL_CLK_MMDC_P0_FAST]	= imx_clk_gate_flags("mmdc_p0_fast", "mmdc_podf", base + 0x74,	20, CLK_IS_CRITICAL);
	clks[IMX6UL_CLK_MMDC_P0_IPG]	= imx_clk_gate2_flags("mmdc_p0_ipg",	"ipg",		base + 0x74,	24, CLK_IS_CRITICAL);
	clks[IMX6UL_CLK_MMDC_P1_IPG]	= imx_clk_gate2("mmdc_p1_ipg",	"ipg",		base + 0x74,	26);
	clks[IMX6UL_CLK_AXI]		= imx_clk_gate_flags("axi",	"axi_podf",	base + 0x74,	28, CLK_IS_CRITICAL);

	/* CCGR4 */
+2 −1
Original line number Diff line number Diff line
@@ -259,7 +259,8 @@
#define IMX6UL_CLK_GPIO3		246
#define IMX6UL_CLK_GPIO4		247
#define IMX6UL_CLK_GPIO5		248
#define IMX6UL_CLK_MMDC_P1_IPG		249

#define IMX6UL_CLK_END			249
#define IMX6UL_CLK_END			250

#endif /* __DT_BINDINGS_CLOCK_IMX6UL_H */