iommu/mediatek: Refine protect memory definition (acb3c92a) · Commits · 戴 / test

The protect memory setting is a little different in the different SoCs. In the register REG_MMU_CTRL_REG(0x110), the TF_PROT(translation fault protect) shift bit is normally 4 while it shift 5 bits only in the mt8173. This patch delete the complex MACRO and use a common if-else instead. Signed-off-by:

Yong Wu <yong.wu@mediatek.com> Reviewed-by:

Evan Green <evgreen@chromium.org> Reviewed-by:

Matthias Brugger <matthias.bgg@gmail.com> Signed-off-by:

Joerg Roedel <jroedel@suse.de>

drivers/iommu/mtk_iommu.c

+6 −7

Original line number	Diff line number	Diff line
		@@ -44,12 +44,9 @@
		#define REG_MMU_DCM_DIS 0x050

		#define REG_MMU_CTRL_REG 0x110
		#define F_MMU_TF_PROT_TO_PROGRAM_ADDR (2 << 4)
		#define F_MMU_PREFETCH_RT_REPLACE_MOD BIT(4)
		#define F_MMU_TF_PROTECT_SEL_SHIFT(data) \
		((data)->plat_data->m4u_plat == M4U_MT2712 ? 4 : 5)
		/* It's named by F_MMU_TF_PROT_SEL in mt2712. */
		#define F_MMU_TF_PROTECT_SEL(prot, data) \
		(((prot) & 0x3) << F_MMU_TF_PROTECT_SEL_SHIFT(data))
		#define F_MMU_TF_PROT_TO_PROGRAM_ADDR_MT8173 (2 << 5)

		#define REG_MMU_IVRP_PADDR 0x114

		@@ -539,9 +536,11 @@ static int mtk_iommu_hw_init(const struct mtk_iommu_data *data)
		return ret;
		}

		regval = F_MMU_TF_PROTECT_SEL(2, data);
		if (data->plat_data->m4u_plat == M4U_MT8173)
		regval \|= F_MMU_PREFETCH_RT_REPLACE_MOD;
		regval = F_MMU_PREFETCH_RT_REPLACE_MOD \|
		F_MMU_TF_PROT_TO_PROGRAM_ADDR_MT8173;
		else
		regval = F_MMU_TF_PROT_TO_PROGRAM_ADDR;
		writel_relaxed(regval, data->base + REG_MMU_CTRL_REG);

		regval = F_L2_MULIT_HIT_EN \|

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