Commit ac7ccfc7 authored by Rafael J. Wysocki's avatar Rafael J. Wysocki
Browse files

Merge branch 'pm-cpufreq' 

* pm-cpufreq:
  cpufreq: Fix up cpufreq_boost_set_sw()
  cpufreq: fix minor typo in struct cpufreq_driver doc comment
  cpufreq: qoriq: Add platform dependencies
  clk: qoriq: add cpufreq platform device
  cpufreq: qoriq: convert to a platform driver
  cpufreq: qcom: fix wrong compatible binding
  cpufreq: imx-cpufreq-dt: support i.MX7ULP
  cpufreq: dt: Add support for r8a7742
  cpufreq: Add i.MX7ULP to cpufreq-dt-platdev blacklist
  cpufreq: omap: Build driver by default for ARCH_OMAP2PLUS
  cpufreq: intel_pstate: Use passive mode by default without HWP
parents f1ecbf79 552abb88

Documentation/admin-guide/pm/intel_pstate.rst

+19 −13
Original line number Diff line number Diff line
@@ -62,9 +62,10 @@ on the capabilities of the processor. 
Active Mode

-----------



This is the default operation mode of ``intel_pstate``.  If it works in this

mode, the ``scaling_driver`` policy attribute in ``sysfs`` for all ``CPUFreq``

policies contains the string "intel_pstate".

This is the default operation mode of ``intel_pstate`` for processors with

hardware-managed P-states (HWP) support.  If it works in this mode, the

``scaling_driver`` policy attribute in ``sysfs`` for all ``CPUFreq`` policies

contains the string "intel_pstate".



In this mode the driver bypasses the scaling governors layer of ``CPUFreq`` and

provides its own scaling algorithms for P-state selection.  Those algorithms
@@ -138,12 +139,13 @@ internal P-state selection logic to be less performance-focused. 
Active Mode Without HWP

~~~~~~~~~~~~~~~~~~~~~~~



This is the default operation mode for processors that do not support the HWP

feature.  It also is used by default with the ``intel_pstate=no_hwp`` argument

in the kernel command line.  However, in this mode ``intel_pstate`` may refuse

to work with the given processor if it does not recognize it.  [Note that

``intel_pstate`` will never refuse to work with any processor with the HWP

feature enabled.]

This operation mode is optional for processors that do not support the HWP

feature or when the ``intel_pstate=no_hwp`` argument is passed to the kernel in

the command line.  The active mode is used in those cases if the

``intel_pstate=active`` argument is passed to the kernel in the command line.

In this mode ``intel_pstate`` may refuse to work with processors that are not

recognized by it.  [Note that ``intel_pstate`` will never refuse to work with

any processor with the HWP feature enabled.]



In this mode ``intel_pstate`` registers utilization update callbacks with the

CPU scheduler in order to run a P-state selection algorithm, either
@@ -188,10 +190,14 @@ is not set. 
Passive Mode

------------



This mode is used if the ``intel_pstate=passive`` argument is passed to the

kernel in the command line (it implies the ``intel_pstate=no_hwp`` setting too).

Like in the active mode without HWP support, in this mode ``intel_pstate`` may

refuse to work with the given processor if it does not recognize it.

This is the default operation mode of ``intel_pstate`` for processors without

hardware-managed P-states (HWP) support.  It is always used if the

``intel_pstate=passive`` argument is passed to the kernel in the command line

regardless of whether or not the given processor supports HWP.  [Note that the

``intel_pstate=no_hwp`` setting implies ``intel_pstate=passive`` if it is used

without ``intel_pstate=active``.]  Like in the active mode without HWP support,

in this mode ``intel_pstate`` may refuse to work with processors that are not

recognized by it.



If the driver works in this mode, the ``scaling_driver`` policy attribute in

``sysfs`` for all ``CPUFreq`` policies contains the string "intel_cpufreq".

drivers/clk/clk-qoriq.c

+27 −3
Original line number Diff line number Diff line
@@ -95,6 +95,7 @@ struct clockgen { 
};



static struct clockgen clockgen;

static bool add_cpufreq_dev __initdata;



static void cg_out(struct clockgen *cg, u32 val, u32 __iomem *reg)

{
@@ -1019,7 +1020,7 @@ static void __init create_muxes(struct clockgen *cg) 
	}

}



static void __init clockgen_init(struct device_node *np);

static void __init _clockgen_init(struct device_node *np, bool legacy);



/*

 * Legacy nodes may get probed before the parent clockgen node.
@@ -1030,7 +1031,7 @@ static void __init clockgen_init(struct device_node *np); 
static void __init legacy_init_clockgen(struct device_node *np)

{

	if (!clockgen.node)

		clockgen_init(of_get_parent(np));

		_clockgen_init(of_get_parent(np), true);

}



/* Legacy node */
@@ -1447,7 +1448,7 @@ static bool __init has_erratum_a4510(void) 
}

#endif



static void __init clockgen_init(struct device_node *np)

static void __init _clockgen_init(struct device_node *np, bool legacy)

{

	int i, ret;

	bool is_old_ls1021a = false;
@@ -1516,12 +1517,35 @@ static void __init clockgen_init(struct device_node *np) 
		       __func__, np, ret);

	}



	/* Don't create cpufreq device for legacy clockgen blocks */

	add_cpufreq_dev = !legacy;



	return;

err:

	iounmap(clockgen.regs);

	clockgen.regs = NULL;

}



static void __init clockgen_init(struct device_node *np)

{

	_clockgen_init(np, false);

}



static int __init clockgen_cpufreq_init(void)

{

	struct platform_device *pdev;



	if (add_cpufreq_dev) {

		pdev = platform_device_register_simple("qoriq-cpufreq", -1,

				NULL, 0);

		if (IS_ERR(pdev))

			pr_err("Couldn't register qoriq-cpufreq err=%ld\n",

				PTR_ERR(pdev));

	}

	return 0;

}

device_initcall(clockgen_cpufreq_init);



CLK_OF_DECLARE(qoriq_clockgen_1, "fsl,qoriq-clockgen-1.0", clockgen_init);

CLK_OF_DECLARE(qoriq_clockgen_2, "fsl,qoriq-clockgen-2.0", clockgen_init);

CLK_OF_DECLARE(qoriq_clockgen_b4420, "fsl,b4420-clockgen", clockgen_init);

drivers/cpufreq/Kconfig

+2 −1
Original line number Diff line number Diff line
@@ -323,7 +323,8 @@ endif 


config QORIQ_CPUFREQ

	tristate "CPU frequency scaling driver for Freescale QorIQ SoCs"

	depends on OF && COMMON_CLK && (PPC_E500MC || ARM || ARM64)

	depends on OF && COMMON_CLK

	depends on PPC_E500MC || SOC_LS1021A || ARCH_LAYERSCAPE || COMPILE_TEST

	select CLK_QORIQ

	help

	  This adds the CPUFreq driver support for Freescale QorIQ SoCs

drivers/cpufreq/Kconfig.arm

+1 −0
Original line number Diff line number Diff line
@@ -317,6 +317,7 @@ config ARM_TEGRA186_CPUFREQ 
config ARM_TI_CPUFREQ

	bool "Texas Instruments CPUFreq support"

	depends on ARCH_OMAP2PLUS

	default ARCH_OMAP2PLUS

	help

	  This driver enables valid OPPs on the running platform based on

	  values contained within the SoC in use. Enable this in order to

drivers/cpufreq/cpufreq-dt-platdev.c

+2 −0
Original line number Diff line number Diff line
@@ -53,6 +53,7 @@ static const struct of_device_id whitelist[] __initconst = { 
	{ .compatible = "renesas,r7s72100", },

	{ .compatible = "renesas,r8a73a4", },

	{ .compatible = "renesas,r8a7740", },

	{ .compatible = "renesas,r8a7742", },

	{ .compatible = "renesas,r8a7743", },

	{ .compatible = "renesas,r8a7744", },

	{ .compatible = "renesas,r8a7745", },
@@ -105,6 +106,7 @@ static const struct of_device_id blacklist[] __initconst = { 
	{ .compatible = "calxeda,highbank", },

	{ .compatible = "calxeda,ecx-2000", },



	{ .compatible = "fsl,imx7ulp", },

	{ .compatible = "fsl,imx7d", },

	{ .compatible = "fsl,imx8mq", },

	{ .compatible = "fsl,imx8mm", },

CRA Git | Maintained and supported by SUSTech CRA and CCSE