Commit ac7b7596 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'pinctrl-v4.13-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl 

Pull pin control updates from Linus Walleij:
 "This is the big bulk of pin control changes for the v4.13 series:

  Core:
   - The documentation is moved over to RST.
   - We now have agreed bindings for enabling input and output buffers
     without actually enabling input and/or output on a pin. We are
     chiseling out some details of pin control electronics.

  New drivers:
   - ZTE ZX
   - Renesas RZA1
   - MIPS Ingenic JZ47xx: also switch over existing drivers in the tree
     to use this pin controller and consolidate earlier spread out code.
   - Microschip MCP23S08: this driver is migrated from the GPIO
     subsystem and totally rewritten to use proper pin control. All
     users are switched over.

  New subdrivers:
   - Renesas R8A7743 and R8A7745.
   - Allwinner Sunxi A83T R_PIO.
   - Marvell MVEBU Armada CP110 and AP806.
   - Intel Cannon Lake PCH.
   - Qualcomm IPQ8074.

  Notable improvements:
   - IRQ support on the Marvell MVEBU Armada 37xx.
   - Meson driver supports HDMI CEC, AO, I2S, SPDIF and PWM.
   - Rockchip driver now supports iomux-route switching for RK3228,
     RK3328 and RK3399.
   - Rockchip A10 and A20 are merged into a single driver.
   - STM32 has improved GPIO support.
   - Samsung Exynos drivers are split per ARMv7 and ARMv8.
   - Marvell MVEBU is converted to use regmap for register access.

  Maintenance:
   - Several Renesas SH-PFC refactorings and updates.
   - Serious code size cut for Mediatek MT7623.
   - Misc janitorial and MAINTAINERS fixes"

* tag 'pinctrl-v4.13-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (137 commits)
  pinctrl: samsung: Remove bogus irq_[un]mask from resource management
  pinctrl: rza1: make structures rza1_gpiochip_template and rza1_pinmux_ops static
  pinctrl: rza1: Remove unneeded wrong check for wrong variable
  pinctrl: qcom: Add ipq8074 pinctrl driver
  pinctrl: freescale: imx7d: make of_device_ids const.
  pinctrl: DT: extend the pinmux property to support integers array
  pinctrl: generic: Add output-enable property
  pinctrl: armada-37xx: Fix number of pin in sdio_sb
  pinctrl: armada-37xx: Fix uart2 group selection register mask
  pinctrl: bcm2835: Avoid warning from __irq_do_set_handler
  pinctrl: sh-pfc: r8a7795: Add PWM support
  MAINTAINERS: Add Qualcomm pinctrl drivers section
  arm: dts: dt-bindings: Add Renesas RZ/A1 pinctrl header
  dt-bindings: pinctrl: Add RZ/A1 bindings doc
  pinctrl: Renesas RZ/A1 pin and gpio controller
  pinctrl: sh-pfc: r8a7792: Add SCIF1 and SCIF2 pin groups
  pinctrl.txt: move it to the driver-api book
  pinctrl: ingenic: checking for NULL instead of IS_ERR()
  pinctrl: uniphier: fix WARN_ON() of pingroups dump on LD20
  pinctrl: uniphier: fix WARN_ON() of pingroups dump on LD11
  ...
parents 4f5dfdd2 3fa53ec2

Documentation/devicetree/bindings/gpio/ingenic,gpio.txt

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+46 −0
Original line number Diff line number Diff line 
Ingenic jz47xx GPIO controller



That the Ingenic GPIO driver node must be a sub-node of the Ingenic pinctrl

driver node.



Required properties:

--------------------



 - compatible: Must contain one of:

    - "ingenic,jz4740-gpio"

    - "ingenic,jz4770-gpio"

    - "ingenic,jz4780-gpio"

 - reg: The GPIO bank number.

 - interrupt-controller: Marks the device node as an interrupt controller.

 - interrupts: Interrupt specifier for the controllers interrupt.

 - #interrupt-cells: Should be 2. Refer to

   ../interrupt-controller/interrupts.txt for more details.

 - gpio-controller: Marks the device node as a GPIO controller.

 - #gpio-cells: Should be 2. The first cell is the GPIO number and the second

    cell specifies GPIO flags, as defined in <dt-bindings/gpio/gpio.h>. Only the

    GPIO_ACTIVE_HIGH and GPIO_ACTIVE_LOW flags are supported.

 - gpio-ranges: Range of pins managed by the GPIO controller. Refer to

   'gpio.txt' in this directory for more details.



Example:

--------



&pinctrl {

	#address-cells = <1>;

	#size-cells = <0>;



	gpa: gpio@0 {

		compatible = "ingenic,jz4740-gpio";

		reg = <0>;



		gpio-controller;

		gpio-ranges = <&pinctrl 0 0 32>;

		#gpio-cells = <2>;



		interrupt-controller;

		#interrupt-cells = <2>;



		interrupt-parent = <&intc>;

		interrupts = <28>;

	};

};

Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt

+2 −0
Original line number Diff line number Diff line
@@ -20,8 +20,10 @@ Required properties: 
  "allwinner,sun9i-a80-pinctrl"

  "allwinner,sun9i-a80-r-pinctrl"

  "allwinner,sun8i-a83t-pinctrl"

  "allwinner,sun8i-a83t-r-pinctrl"

  "allwinner,sun8i-h3-pinctrl"

  "allwinner,sun8i-h3-r-pinctrl"

  "allwinner,sun8i-r40-pinctrl"

  "allwinner,sun50i-a64-pinctrl"

  "allwinner,sun50i-a64-r-pinctrl"

  "allwinner,sun50i-h5-pinctrl"

Documentation/devicetree/bindings/pinctrl/ingenic,pinctrl.txt

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Original line number Diff line number Diff line 
Ingenic jz47xx pin controller



Please refer to pinctrl-bindings.txt in this directory for details of the

common pinctrl bindings used by client devices, including the meaning of the

phrase "pin configuration node".



For the jz47xx SoCs, pin control is tightly bound with GPIO ports. All pins may

be used as GPIOs, multiplexed device functions are configured within the

GPIO port configuration registers and it is typical to refer to pins using the

naming scheme "PxN" where x is a character identifying the GPIO port with

which the pin is associated and N is an integer from 0 to 31 identifying the

pin within that GPIO port. For example PA0 is the first pin in GPIO port A, and

PB31 is the last pin in GPIO port B. The jz4740 contains 4 GPIO ports, PA to

PD, for a total of 128 pins. The jz4780 contains 6 GPIO ports, PA to PF, for a

total of 192 pins.





Required properties:

--------------------



 - compatible: One of:

    - "ingenic,jz4740-pinctrl"

    - "ingenic,jz4770-pinctrl"

    - "ingenic,jz4780-pinctrl"

 - reg: Address range of the pinctrl registers.





GPIO sub-nodes

--------------



The pinctrl node can have optional sub-nodes for the Ingenic GPIO driver;

please refer to ../gpio/ingenic,gpio.txt.





Example:

--------



pinctrl: pin-controller@10010000 {

	compatible = "ingenic,jz4740-pinctrl";

	reg = <0x10010000 0x400>;

};

Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt

+16 −9
Original line number Diff line number Diff line
@@ -204,21 +204,22 @@ each single pin the number of required sub-nodes containing "pin" and 
maintain.



For cases like this, the pin controller driver may use the pinmux helper

property, where the pin identifier is packed with mux configuration settings

in a single integer.

property, where the pin identifier is provided with mux configuration settings

in a pinmux group. A pinmux group consists of the pin identifier and mux

settings represented as a single integer or an array of integers.



The pinmux property accepts an array of integers, each of them describing

The pinmux property accepts an array of pinmux groups, each of them describing

a single pin multiplexing configuration.



pincontroller {

	state_0_node_a {

		pinmux = <PIN_ID_AND_MUX>, <PIN_ID_AND_MUX>, ...;

		pinmux = <PINMUX_GROUP>, <PINMUX_GROUP>, ...;

	};

};



Each individual pin controller driver bindings documentation shall specify

how those values (pin IDs and pin multiplexing configuration) are defined and

assembled together.

how pin IDs and pin multiplexing configuration are defined and assembled

together in a pinmux group.



== Generic pin configuration node content ==
@@ -251,14 +252,20 @@ drive-push-pull - drive actively high and low 
drive-open-drain	- drive with open drain

drive-open-source	- drive with open source

drive-strength		- sink or source at most X mA

input-enable		- enable input on pin (no effect on output)

input-disable		- disable input on pin (no effect on output)

input-enable		- enable input on pin (no effect on output, such as

			  enabling an input buffer)

input-disable		- disable input on pin (no effect on output, such as

			  disabling an input buffer)

input-schmitt-enable	- enable schmitt-trigger mode

input-schmitt-disable	- disable schmitt-trigger mode

input-debounce		- debounce mode with debound time X

power-source		- select between different power supplies

low-power-enable	- enable low power mode

low-power-disable	- disable low power mode

output-disable		- disable output on a pin (such as disable an output

			  buffer)

output-enable		- enable output on a pin without actively driving it

			  (such as enabling an output buffer)

output-low		- set the pin to output mode with low level

output-high		- set the pin to output mode with high level

slew-rate		- set the slew rate
@@ -300,7 +307,7 @@ arguments are described below. 
- pinmux takes a list of pin IDs and mux settings as required argument. The

  specific bindings for the hardware defines:

  - How pin IDs and mux settings are defined and assembled together in a single

    integer.

    integer or an array of integers.



- bias-pull-up, -down and -pin-default take as optional argument on hardware

  supporting it the pull strength in Ohm. bias-disable will disable the pull.

Documentation/devicetree/bindings/pinctrl/pinctrl-zx.txt

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* ZTE ZX Pin Controller



The pin controller on ZTE ZX platforms is kinda of hybrid.  It consists of

a main controller and an auxiliary one.  For example, on ZX296718 SoC, the

main controller is TOP_PMM and the auxiliary one is AON_IOCFG.  Both

controllers work together to control pin multiplexing and configuration in

the way illustrated as below.





           GMII_RXD3 ---+

                        |

             DVI1_HS ---+----------------------------- GMII_RXD3 (TOP pin)

                        |

             BGPIO16 ---+                               ^

                                                        | pinconf

                        ^                               |

                        | pinmux                        |

                        |                               |



                   TOP_PMM (main)           AON_IOCFG (aux)



                        |                       |       |

                        |                pinmux |       |

                        | pinmux                v       |

                        v                               | pinconf

                                    KEY_ROW2 ---+       v

        PORT1_LCD_TE ---+                       |

                        |            AGPIO10 ---+------ KEY_ROW2 (AON pin)

          I2S0_DOUT3 ---+                       |

                        |-----------------------+

            PWM_OUT3 ---+

                        |

             VGA_VS1 ---+





For most of pins like GMII_RXD3 in the figure, the pinmux function is

controlled by TOP_PMM block only, and this type of pins are meant by term

'TOP pins'.  For pins like KEY_ROW2, the pinmux is controlled by both

TOP_PMM and AON_IOCFG blocks, as the available multiplexing functions for

the pin spread in both controllers.  This type of pins are called 'AON pins'.

Though pinmux implementation is quite different, pinconf is same for both

types of pins.  Both are controlled by auxiliary controller, i.e. AON_IOCFG

on ZX296718.



Required properties:

- compatible: should be "zte,zx296718-pmm".

- reg: the register physical address and length.

- zte,auxiliary-controller: phandle to the auxiliary pin controller which

  implements pinmux for AON pins and pinconf for all pins.



The following pin configuration are supported. Please refer to

pinctrl-bindings.txt in this directory for more details of the common

pinctrl bindings used by client devices.



- bias-pull-up

- bias-pull-down

- drive-strength

- input-enable

- slew-rate



Examples:



iocfg: pin-controller@119000 {

	compatible = "zte,zx296718-iocfg";

	reg = <0x119000 0x1000>;

};



pmm: pin-controller@1462000 {

	compatible = "zte,zx296718-pmm";

	reg = <0x1462000 0x1000>;

	zte,auxiliary-controller = <&iocfg>;

};



&pmm {

	vga_pins: vga {

		pins = "KEY_COL1", "KEY_COL2", "KEY_ROW1", "KEY_ROW2";

		function = "VGA";

	};

};



&vga {

	pinctrl-names = "default";

	pinctrl-0 = <&vga_pins>;

	status = "okay";

};

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