Commit ac78bd72 authored by Pu Wen's avatar Pu Wen Committed by Borislav Petkov
Browse files

x86/mce: Add Hygon Dhyana support to the MCA infrastructure 



The machine check architecture for Hygon Dhyana CPU is similar to the
AMD family 17h one. Add vendor checking for Hygon Dhyana to share the
code path of AMD family 17h.

Signed-off-by: default avatarPu Wen <puwen@hygon.cn>
Signed-off-by: default avatarBorislav Petkov <bp@suse.de>
Reviewed-by: default avatarBorislav Petkov <bp@suse.de>
Cc: tglx@linutronix.de
Cc: mingo@redhat.com
Cc: hpa@zytor.com
Cc: tony.luck@intel.com
Cc: thomas.lendacky@amd.com
Cc: linux-edac@vger.kernel.org
Link: https://lkml.kernel.org/r/87d8a4f16bdea0bfe0c0cf2e4a8d2c2a99b1055c.1537533369.git.puwen@hygon.cn
parent 1a576b23

arch/x86/include/asm/mce.h

+2 −0
Original line number Diff line number Diff line
@@ -214,6 +214,8 @@ static inline void mce_amd_feature_init(struct cpuinfo_x86 *c) { } 
static inline int umc_normaddr_to_sysaddr(u64 norm_addr, u16 nid, u8 umc, u64 *sys_addr) { return -EINVAL; };

#endif



static inline void mce_hygon_feature_init(struct cpuinfo_x86 *c) { return mce_amd_feature_init(c); }



int mce_available(struct cpuinfo_x86 *c);

bool mce_is_memory_error(struct mce *m);

arch/x86/kernel/cpu/mcheck/mce-severity.c

+2 −1
Original line number Diff line number Diff line
@@ -336,7 +336,8 @@ int (*mce_severity)(struct mce *m, int tolerant, char **msg, bool is_excp) = 


void __init mcheck_vendor_init_severity(void)

{

	if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD)

	if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD ||

	    boot_cpu_data.x86_vendor == X86_VENDOR_HYGON)

		mce_severity = mce_severity_amd;

}

arch/x86/kernel/cpu/mcheck/mce.c

+15 −5
Original line number Diff line number Diff line
@@ -270,7 +270,7 @@ static void print_mce(struct mce *m) 
{

	__print_mce(m);



	if (m->cpuvendor != X86_VENDOR_AMD)

	if (m->cpuvendor != X86_VENDOR_AMD && m->cpuvendor != X86_VENDOR_HYGON)

		pr_emerg_ratelimited(HW_ERR "Run the above through 'mcelog --ascii'\n");

}
@@ -508,9 +508,9 @@ static int mce_usable_address(struct mce *m) 


bool mce_is_memory_error(struct mce *m)

{

	if (m->cpuvendor == X86_VENDOR_AMD) {

	if (m->cpuvendor == X86_VENDOR_AMD ||

	    m->cpuvendor == X86_VENDOR_HYGON) {

		return amd_mce_is_memory_error(m);



	} else if (m->cpuvendor == X86_VENDOR_INTEL) {

		/*

		 * Intel SDM Volume 3B - 15.9.2 Compound Error Codes
@@ -539,6 +539,9 @@ static bool mce_is_correctable(struct mce *m) 
	if (m->cpuvendor == X86_VENDOR_AMD && m->status & MCI_STATUS_DEFERRED)

		return false;



	if (m->cpuvendor == X86_VENDOR_HYGON && m->status & MCI_STATUS_DEFERRED)

		return false;



	if (m->status & MCI_STATUS_UC)

		return false;
@@ -1705,7 +1708,7 @@ static int __mcheck_cpu_ancient_init(struct cpuinfo_x86 *c) 
 */

static void __mcheck_cpu_init_early(struct cpuinfo_x86 *c)

{

	if (c->x86_vendor == X86_VENDOR_AMD) {

	if (c->x86_vendor == X86_VENDOR_AMD || c->x86_vendor == X86_VENDOR_HYGON) {

		mce_flags.overflow_recov = !!cpu_has(c, X86_FEATURE_OVERFLOW_RECOV);

		mce_flags.succor	 = !!cpu_has(c, X86_FEATURE_SUCCOR);

		mce_flags.smca		 = !!cpu_has(c, X86_FEATURE_SMCA);
@@ -1746,6 +1749,11 @@ static void __mcheck_cpu_init_vendor(struct cpuinfo_x86 *c) 
		mce_amd_feature_init(c);

		break;

		}



	case X86_VENDOR_HYGON:

		mce_hygon_feature_init(c);

		break;



	case X86_VENDOR_CENTAUR:

		mce_centaur_feature_init(c);

		break;
@@ -1971,12 +1979,14 @@ static void mce_disable_error_reporting(void) 
static void vendor_disable_error_reporting(void)

{

	/*

	 * Don't clear on Intel or AMD CPUs. Some of these MSRs are socket-wide.

	 * Don't clear on Intel or AMD or Hygon CPUs. Some of these MSRs

	 * are socket-wide.

	 * Disabling them for just a single offlined CPU is bad, since it will

	 * inhibit reporting for all shared resources on the socket like the

	 * last level cache (LLC), the integrated memory controller (iMC), etc.

	 */

	if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL ||

	    boot_cpu_data.x86_vendor == X86_VENDOR_HYGON ||

	    boot_cpu_data.x86_vendor == X86_VENDOR_AMD)

		return;

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