Commit ac6183ae authored by Tomer Tayar's avatar Tomer Tayar Committed by Oded Gabbay
Browse files

habanalabs: Update the device idle check 



The patch updates the device idle check:
- Add reading the DMA core status register, because it is possible that
  a QMAN has finished its work but the DMA itself is still running.
- Remove the MME shadow status check, as the MME ARCH status register
  includes the status of all MME shadows.

Signed-off-by: default avatarTomer Tayar <ttayar@habana.ai>
Reviewed-by: default avatarOded Gabbay <oded.gabbay@gmail.com>
Signed-off-by: default avatarOded Gabbay <oded.gabbay@gmail.com>
parent 4a0ce776

drivers/misc/habanalabs/goya/goya.c

+6 −4
Original line number Diff line number Diff line
@@ -4893,17 +4893,22 @@ int goya_armcp_info_get(struct hl_device *hdev) 


static bool goya_is_device_idle(struct hl_device *hdev, char *buf, size_t size)

{

	u64 offset, dma_qm_reg, tpc_qm_reg, tpc_cmdq_reg, tpc_cfg_reg;

	u64 offset, dma_qm_reg, tpc_qm_reg, tpc_cmdq_reg, tpc_cfg_reg,

		dma_core_sts;

	int i;



	offset = mmDMA_QM_1_GLBL_STS0 - mmDMA_QM_0_GLBL_STS0;



	for (i = 0 ; i < DMA_MAX_NUM ; i++) {

		dma_qm_reg = mmDMA_QM_0_GLBL_STS0 + i * offset;

		dma_core_sts = mmDMA_CH_0_STS0 + i * offset;



		if ((RREG32(dma_qm_reg) & DMA_QM_IDLE_MASK) !=

				DMA_QM_IDLE_MASK)

			return HL_ENG_BUSY(buf, size, "DMA%d_QM", i);



		if (RREG32(dma_core_sts) & DMA_CH_0_STS0_DMA_BUSY_MASK)

			return HL_ENG_BUSY(buf, size, "DMA%d_CORE", i);

	}



	offset = mmTPC1_QM_GLBL_STS0 - mmTPC0_QM_GLBL_STS0;
@@ -4938,9 +4943,6 @@ static bool goya_is_device_idle(struct hl_device *hdev, char *buf, size_t size) 
			MME_ARCH_IDLE_MASK)

		return HL_ENG_BUSY(buf, size, "MME_ARCH");



	if (RREG32(mmMME_SHADOW_0_STATUS) & MME_SHADOW_IDLE_MASK)

		return HL_ENG_BUSY(buf, size, "MME");



	return true;

}

drivers/misc/habanalabs/include/goya/asic_reg/dma_ch_0_masks.h

0 → 100644
+418 −0
Original line number Diff line number Diff line 
/* SPDX-License-Identifier: GPL-2.0

 *

 * Copyright 2016-2018 HabanaLabs, Ltd.

 * All Rights Reserved.

 *

 */



/************************************

 ** This is an auto-generated file **

 **       DO NOT EDIT BELOW        **

 ************************************/



#ifndef ASIC_REG_DMA_CH_0_MASKS_H_

#define ASIC_REG_DMA_CH_0_MASKS_H_



/*

 *****************************************

 *   DMA_CH_0 (Prototype: DMA_CH)

 *****************************************

 */



/* DMA_CH_0_CFG0 */

#define DMA_CH_0_CFG0_RD_MAX_OUTSTAND_SHIFT                          0

#define DMA_CH_0_CFG0_RD_MAX_OUTSTAND_MASK                           0x3FF

#define DMA_CH_0_CFG0_WR_MAX_OUTSTAND_SHIFT                          16

#define DMA_CH_0_CFG0_WR_MAX_OUTSTAND_MASK                           0xFFF0000



/* DMA_CH_0_CFG1 */

#define DMA_CH_0_CFG1_RD_BUF_MAX_SIZE_SHIFT                          0

#define DMA_CH_0_CFG1_RD_BUF_MAX_SIZE_MASK                           0x3FF



/* DMA_CH_0_ERRMSG_ADDR_LO */

#define DMA_CH_0_ERRMSG_ADDR_LO_VAL_SHIFT                            0

#define DMA_CH_0_ERRMSG_ADDR_LO_VAL_MASK                             0xFFFFFFFF



/* DMA_CH_0_ERRMSG_ADDR_HI */

#define DMA_CH_0_ERRMSG_ADDR_HI_VAL_SHIFT                            0

#define DMA_CH_0_ERRMSG_ADDR_HI_VAL_MASK                             0xFFFFFFFF



/* DMA_CH_0_ERRMSG_WDATA */

#define DMA_CH_0_ERRMSG_WDATA_VAL_SHIFT                              0

#define DMA_CH_0_ERRMSG_WDATA_VAL_MASK                               0xFFFFFFFF



/* DMA_CH_0_RD_COMP_ADDR_LO */

#define DMA_CH_0_RD_COMP_ADDR_LO_VAL_SHIFT                           0

#define DMA_CH_0_RD_COMP_ADDR_LO_VAL_MASK                            0xFFFFFFFF



/* DMA_CH_0_RD_COMP_ADDR_HI */

#define DMA_CH_0_RD_COMP_ADDR_HI_VAL_SHIFT                           0

#define DMA_CH_0_RD_COMP_ADDR_HI_VAL_MASK                            0xFFFFFFFF



/* DMA_CH_0_RD_COMP_WDATA */

#define DMA_CH_0_RD_COMP_WDATA_VAL_SHIFT                             0

#define DMA_CH_0_RD_COMP_WDATA_VAL_MASK                              0xFFFFFFFF



/* DMA_CH_0_WR_COMP_ADDR_LO */

#define DMA_CH_0_WR_COMP_ADDR_LO_VAL_SHIFT                           0

#define DMA_CH_0_WR_COMP_ADDR_LO_VAL_MASK                            0xFFFFFFFF



/* DMA_CH_0_WR_COMP_ADDR_HI */

#define DMA_CH_0_WR_COMP_ADDR_HI_VAL_SHIFT                           0

#define DMA_CH_0_WR_COMP_ADDR_HI_VAL_MASK                            0xFFFFFFFF



/* DMA_CH_0_WR_COMP_WDATA */

#define DMA_CH_0_WR_COMP_WDATA_VAL_SHIFT                             0

#define DMA_CH_0_WR_COMP_WDATA_VAL_MASK                              0xFFFFFFFF



/* DMA_CH_0_LDMA_SRC_ADDR_LO */

#define DMA_CH_0_LDMA_SRC_ADDR_LO_VAL_SHIFT                          0

#define DMA_CH_0_LDMA_SRC_ADDR_LO_VAL_MASK                           0xFFFFFFFF



/* DMA_CH_0_LDMA_SRC_ADDR_HI */

#define DMA_CH_0_LDMA_SRC_ADDR_HI_VAL_SHIFT                          0

#define DMA_CH_0_LDMA_SRC_ADDR_HI_VAL_MASK                           0xFFFFFFFF



/* DMA_CH_0_LDMA_DST_ADDR_LO */

#define DMA_CH_0_LDMA_DST_ADDR_LO_VAL_SHIFT                          0

#define DMA_CH_0_LDMA_DST_ADDR_LO_VAL_MASK                           0xFFFFFFFF



/* DMA_CH_0_LDMA_DST_ADDR_HI */

#define DMA_CH_0_LDMA_DST_ADDR_HI_VAL_SHIFT                          0

#define DMA_CH_0_LDMA_DST_ADDR_HI_VAL_MASK                           0xFFFFFFFF



/* DMA_CH_0_LDMA_TSIZE */

#define DMA_CH_0_LDMA_TSIZE_VAL_SHIFT                                0

#define DMA_CH_0_LDMA_TSIZE_VAL_MASK                                 0xFFFFFFFF



/* DMA_CH_0_COMIT_TRANSFER */

#define DMA_CH_0_COMIT_TRANSFER_PCI_UPS_WKORDR_SHIFT                 0

#define DMA_CH_0_COMIT_TRANSFER_PCI_UPS_WKORDR_MASK                  0x1

#define DMA_CH_0_COMIT_TRANSFER_RD_COMP_EN_SHIFT                     1

#define DMA_CH_0_COMIT_TRANSFER_RD_COMP_EN_MASK                      0x2

#define DMA_CH_0_COMIT_TRANSFER_WR_COMP_EN_SHIFT                     2

#define DMA_CH_0_COMIT_TRANSFER_WR_COMP_EN_MASK                      0x4

#define DMA_CH_0_COMIT_TRANSFER_NOSNOOP_SHIFT                        3

#define DMA_CH_0_COMIT_TRANSFER_NOSNOOP_MASK                         0x8

#define DMA_CH_0_COMIT_TRANSFER_SRC_ADDR_INC_DIS_SHIFT               4

#define DMA_CH_0_COMIT_TRANSFER_SRC_ADDR_INC_DIS_MASK                0x10

#define DMA_CH_0_COMIT_TRANSFER_DST_ADDR_INC_DIS_SHIFT               5

#define DMA_CH_0_COMIT_TRANSFER_DST_ADDR_INC_DIS_MASK                0x20

#define DMA_CH_0_COMIT_TRANSFER_MEM_SET_SHIFT                        6

#define DMA_CH_0_COMIT_TRANSFER_MEM_SET_MASK                         0x40

#define DMA_CH_0_COMIT_TRANSFER_MOD_TENSOR_SHIFT                     15

#define DMA_CH_0_COMIT_TRANSFER_MOD_TENSOR_MASK                      0x8000

#define DMA_CH_0_COMIT_TRANSFER_CTL_SHIFT                            16

#define DMA_CH_0_COMIT_TRANSFER_CTL_MASK                             0xFFFF0000



/* DMA_CH_0_STS0 */

#define DMA_CH_0_STS0_DMA_BUSY_SHIFT                                 0

#define DMA_CH_0_STS0_DMA_BUSY_MASK                                  0x1

#define DMA_CH_0_STS0_RD_STS_CTX_FULL_SHIFT                          1

#define DMA_CH_0_STS0_RD_STS_CTX_FULL_MASK                           0x2

#define DMA_CH_0_STS0_WR_STS_CTX_FULL_SHIFT                          2

#define DMA_CH_0_STS0_WR_STS_CTX_FULL_MASK                           0x4



/* DMA_CH_0_STS1 */

#define DMA_CH_0_STS1_RD_STS_CTX_CNT_SHIFT                           0

#define DMA_CH_0_STS1_RD_STS_CTX_CNT_MASK                            0xFFFFFFFF



/* DMA_CH_0_STS2 */

#define DMA_CH_0_STS2_WR_STS_CTX_CNT_SHIFT                           0

#define DMA_CH_0_STS2_WR_STS_CTX_CNT_MASK                            0xFFFFFFFF



/* DMA_CH_0_STS3 */

#define DMA_CH_0_STS3_RD_STS_TRN_CNT_SHIFT                           0

#define DMA_CH_0_STS3_RD_STS_TRN_CNT_MASK                            0xFFFFFFFF



/* DMA_CH_0_STS4 */

#define DMA_CH_0_STS4_WR_STS_TRN_CNT_SHIFT                           0

#define DMA_CH_0_STS4_WR_STS_TRN_CNT_MASK                            0xFFFFFFFF



/* DMA_CH_0_SRC_ADDR_LO_STS */

#define DMA_CH_0_SRC_ADDR_LO_STS_VAL_SHIFT                           0

#define DMA_CH_0_SRC_ADDR_LO_STS_VAL_MASK                            0xFFFFFFFF



/* DMA_CH_0_SRC_ADDR_HI_STS */

#define DMA_CH_0_SRC_ADDR_HI_STS_VAL_SHIFT                           0

#define DMA_CH_0_SRC_ADDR_HI_STS_VAL_MASK                            0xFFFFFFFF



/* DMA_CH_0_SRC_TSIZE_STS */

#define DMA_CH_0_SRC_TSIZE_STS_VAL_SHIFT                             0

#define DMA_CH_0_SRC_TSIZE_STS_VAL_MASK                              0xFFFFFFFF



/* DMA_CH_0_DST_ADDR_LO_STS */

#define DMA_CH_0_DST_ADDR_LO_STS_VAL_SHIFT                           0

#define DMA_CH_0_DST_ADDR_LO_STS_VAL_MASK                            0xFFFFFFFF



/* DMA_CH_0_DST_ADDR_HI_STS */

#define DMA_CH_0_DST_ADDR_HI_STS_VAL_SHIFT                           0

#define DMA_CH_0_DST_ADDR_HI_STS_VAL_MASK                            0xFFFFFFFF



/* DMA_CH_0_DST_TSIZE_STS */

#define DMA_CH_0_DST_TSIZE_STS_VAL_SHIFT                             0

#define DMA_CH_0_DST_TSIZE_STS_VAL_MASK                              0xFFFFFFFF



/* DMA_CH_0_RD_RATE_LIM_EN */

#define DMA_CH_0_RD_RATE_LIM_EN_VAL_SHIFT                            0

#define DMA_CH_0_RD_RATE_LIM_EN_VAL_MASK                             0x1



/* DMA_CH_0_RD_RATE_LIM_RST_TOKEN */

#define DMA_CH_0_RD_RATE_LIM_RST_TOKEN_VAL_SHIFT                     0

#define DMA_CH_0_RD_RATE_LIM_RST_TOKEN_VAL_MASK                      0xFFFF



/* DMA_CH_0_RD_RATE_LIM_SAT */

#define DMA_CH_0_RD_RATE_LIM_SAT_VAL_SHIFT                           0

#define DMA_CH_0_RD_RATE_LIM_SAT_VAL_MASK                            0xFFFF



/* DMA_CH_0_RD_RATE_LIM_TOUT */

#define DMA_CH_0_RD_RATE_LIM_TOUT_VAL_SHIFT                          0

#define DMA_CH_0_RD_RATE_LIM_TOUT_VAL_MASK                           0x7FFFFFFF



/* DMA_CH_0_WR_RATE_LIM_EN */

#define DMA_CH_0_WR_RATE_LIM_EN_VAL_SHIFT                            0

#define DMA_CH_0_WR_RATE_LIM_EN_VAL_MASK                             0x1



/* DMA_CH_0_WR_RATE_LIM_RST_TOKEN */

#define DMA_CH_0_WR_RATE_LIM_RST_TOKEN_VAL_SHIFT                     0

#define DMA_CH_0_WR_RATE_LIM_RST_TOKEN_VAL_MASK                      0xFFFF



/* DMA_CH_0_WR_RATE_LIM_SAT */

#define DMA_CH_0_WR_RATE_LIM_SAT_VAL_SHIFT                           0

#define DMA_CH_0_WR_RATE_LIM_SAT_VAL_MASK                            0xFFFF



/* DMA_CH_0_WR_RATE_LIM_TOUT */

#define DMA_CH_0_WR_RATE_LIM_TOUT_VAL_SHIFT                          0

#define DMA_CH_0_WR_RATE_LIM_TOUT_VAL_MASK                           0x7FFFFFFF



/* DMA_CH_0_CFG2 */

#define DMA_CH_0_CFG2_FORCE_WORD_SHIFT                               0

#define DMA_CH_0_CFG2_FORCE_WORD_MASK                                0x1



/* DMA_CH_0_TDMA_CTL */

#define DMA_CH_0_TDMA_CTL_DTYPE_SHIFT                                0

#define DMA_CH_0_TDMA_CTL_DTYPE_MASK                                 0x7



/* DMA_CH_0_TDMA_SRC_BASE_ADDR_LO */

#define DMA_CH_0_TDMA_SRC_BASE_ADDR_LO_VAL_SHIFT                     0

#define DMA_CH_0_TDMA_SRC_BASE_ADDR_LO_VAL_MASK                      0xFFFFFFFF



/* DMA_CH_0_TDMA_SRC_BASE_ADDR_HI */

#define DMA_CH_0_TDMA_SRC_BASE_ADDR_HI_VAL_SHIFT                     0

#define DMA_CH_0_TDMA_SRC_BASE_ADDR_HI_VAL_MASK                      0xFFFFFFFF



/* DMA_CH_0_TDMA_SRC_ROI_BASE_0 */

#define DMA_CH_0_TDMA_SRC_ROI_BASE_0_VAL_SHIFT                       0

#define DMA_CH_0_TDMA_SRC_ROI_BASE_0_VAL_MASK                        0xFFFFFFFF



/* DMA_CH_0_TDMA_SRC_ROI_SIZE_0 */

#define DMA_CH_0_TDMA_SRC_ROI_SIZE_0_VAL_SHIFT                       0

#define DMA_CH_0_TDMA_SRC_ROI_SIZE_0_VAL_MASK                        0xFFFFFFFF



/* DMA_CH_0_TDMA_SRC_VALID_ELEMENTS_0 */

#define DMA_CH_0_TDMA_SRC_VALID_ELEMENTS_0_VAL_SHIFT                 0

#define DMA_CH_0_TDMA_SRC_VALID_ELEMENTS_0_VAL_MASK                  0xFFFFFFFF



/* DMA_CH_0_TDMA_SRC_START_OFFSET_0 */

#define DMA_CH_0_TDMA_SRC_START_OFFSET_0_VAL_SHIFT                   0

#define DMA_CH_0_TDMA_SRC_START_OFFSET_0_VAL_MASK                    0xFFFFFFFF



/* DMA_CH_0_TDMA_SRC_STRIDE_0 */

#define DMA_CH_0_TDMA_SRC_STRIDE_0_VAL_SHIFT                         0

#define DMA_CH_0_TDMA_SRC_STRIDE_0_VAL_MASK                          0xFFFFFFFF



/* DMA_CH_0_TDMA_SRC_ROI_BASE_1 */

#define DMA_CH_0_TDMA_SRC_ROI_BASE_1_VAL_SHIFT                       0

#define DMA_CH_0_TDMA_SRC_ROI_BASE_1_VAL_MASK                        0xFFFFFFFF



/* DMA_CH_0_TDMA_SRC_ROI_SIZE_1 */

#define DMA_CH_0_TDMA_SRC_ROI_SIZE_1_VAL_SHIFT                       0

#define DMA_CH_0_TDMA_SRC_ROI_SIZE_1_VAL_MASK                        0xFFFFFFFF



/* DMA_CH_0_TDMA_SRC_VALID_ELEMENTS_1 */

#define DMA_CH_0_TDMA_SRC_VALID_ELEMENTS_1_VAL_SHIFT                 0

#define DMA_CH_0_TDMA_SRC_VALID_ELEMENTS_1_VAL_MASK                  0xFFFFFFFF



/* DMA_CH_0_TDMA_SRC_START_OFFSET_1 */

#define DMA_CH_0_TDMA_SRC_START_OFFSET_1_VAL_SHIFT                   0

#define DMA_CH_0_TDMA_SRC_START_OFFSET_1_VAL_MASK                    0xFFFFFFFF



/* DMA_CH_0_TDMA_SRC_STRIDE_1 */

#define DMA_CH_0_TDMA_SRC_STRIDE_1_VAL_SHIFT                         0

#define DMA_CH_0_TDMA_SRC_STRIDE_1_VAL_MASK                          0xFFFFFFFF



/* DMA_CH_0_TDMA_SRC_ROI_BASE_2 */

#define DMA_CH_0_TDMA_SRC_ROI_BASE_2_VAL_SHIFT                       0

#define DMA_CH_0_TDMA_SRC_ROI_BASE_2_VAL_MASK                        0xFFFFFFFF



/* DMA_CH_0_TDMA_SRC_ROI_SIZE_2 */

#define DMA_CH_0_TDMA_SRC_ROI_SIZE_2_VAL_SHIFT                       0

#define DMA_CH_0_TDMA_SRC_ROI_SIZE_2_VAL_MASK                        0xFFFFFFFF



/* DMA_CH_0_TDMA_SRC_VALID_ELEMENTS_2 */

#define DMA_CH_0_TDMA_SRC_VALID_ELEMENTS_2_VAL_SHIFT                 0

#define DMA_CH_0_TDMA_SRC_VALID_ELEMENTS_2_VAL_MASK                  0xFFFFFFFF



/* DMA_CH_0_TDMA_SRC_START_OFFSET_2 */

#define DMA_CH_0_TDMA_SRC_START_OFFSET_2_VAL_SHIFT                   0

#define DMA_CH_0_TDMA_SRC_START_OFFSET_2_VAL_MASK                    0xFFFFFFFF



/* DMA_CH_0_TDMA_SRC_STRIDE_2 */

#define DMA_CH_0_TDMA_SRC_STRIDE_2_VAL_SHIFT                         0

#define DMA_CH_0_TDMA_SRC_STRIDE_2_VAL_MASK                          0xFFFFFFFF



/* DMA_CH_0_TDMA_SRC_ROI_BASE_3 */

#define DMA_CH_0_TDMA_SRC_ROI_BASE_3_VAL_SHIFT                       0

#define DMA_CH_0_TDMA_SRC_ROI_BASE_3_VAL_MASK                        0xFFFFFFFF



/* DMA_CH_0_TDMA_SRC_ROI_SIZE_3 */

#define DMA_CH_0_TDMA_SRC_ROI_SIZE_3_VAL_SHIFT                       0

#define DMA_CH_0_TDMA_SRC_ROI_SIZE_3_VAL_MASK                        0xFFFFFFFF



/* DMA_CH_0_TDMA_SRC_VALID_ELEMENTS_3 */

#define DMA_CH_0_TDMA_SRC_VALID_ELEMENTS_3_VAL_SHIFT                 0

#define DMA_CH_0_TDMA_SRC_VALID_ELEMENTS_3_VAL_MASK                  0xFFFFFFFF



/* DMA_CH_0_TDMA_SRC_START_OFFSET_3 */

#define DMA_CH_0_TDMA_SRC_START_OFFSET_3_VAL_SHIFT                   0

#define DMA_CH_0_TDMA_SRC_START_OFFSET_3_VAL_MASK                    0xFFFFFFFF



/* DMA_CH_0_TDMA_SRC_STRIDE_3 */

#define DMA_CH_0_TDMA_SRC_STRIDE_3_VAL_SHIFT                         0

#define DMA_CH_0_TDMA_SRC_STRIDE_3_VAL_MASK                          0xFFFFFFFF



/* DMA_CH_0_TDMA_SRC_ROI_BASE_4 */

#define DMA_CH_0_TDMA_SRC_ROI_BASE_4_VAL_SHIFT                       0

#define DMA_CH_0_TDMA_SRC_ROI_BASE_4_VAL_MASK                        0xFFFFFFFF



/* DMA_CH_0_TDMA_SRC_ROI_SIZE_4 */

#define DMA_CH_0_TDMA_SRC_ROI_SIZE_4_VAL_SHIFT                       0

#define DMA_CH_0_TDMA_SRC_ROI_SIZE_4_VAL_MASK                        0xFFFFFFFF



/* DMA_CH_0_TDMA_SRC_VALID_ELEMENTS_4 */

#define DMA_CH_0_TDMA_SRC_VALID_ELEMENTS_4_VAL_SHIFT                 0

#define DMA_CH_0_TDMA_SRC_VALID_ELEMENTS_4_VAL_MASK                  0xFFFFFFFF



/* DMA_CH_0_TDMA_SRC_START_OFFSET_4 */

#define DMA_CH_0_TDMA_SRC_START_OFFSET_4_VAL_SHIFT                   0

#define DMA_CH_0_TDMA_SRC_START_OFFSET_4_VAL_MASK                    0xFFFFFFFF



/* DMA_CH_0_TDMA_SRC_STRIDE_4 */

#define DMA_CH_0_TDMA_SRC_STRIDE_4_VAL_SHIFT                         0

#define DMA_CH_0_TDMA_SRC_STRIDE_4_VAL_MASK                          0xFFFFFFFF



/* DMA_CH_0_TDMA_DST_BASE_ADDR_LO */

#define DMA_CH_0_TDMA_DST_BASE_ADDR_LO_VAL_SHIFT                     0

#define DMA_CH_0_TDMA_DST_BASE_ADDR_LO_VAL_MASK                      0xFFFFFFFF



/* DMA_CH_0_TDMA_DST_BASE_ADDR_HI */

#define DMA_CH_0_TDMA_DST_BASE_ADDR_HI_VAL_SHIFT                     0

#define DMA_CH_0_TDMA_DST_BASE_ADDR_HI_VAL_MASK                      0xFFFFFFFF



/* DMA_CH_0_TDMA_DST_ROI_BASE_0 */

#define DMA_CH_0_TDMA_DST_ROI_BASE_0_VAL_SHIFT                       0

#define DMA_CH_0_TDMA_DST_ROI_BASE_0_VAL_MASK                        0xFFFFFFFF



/* DMA_CH_0_TDMA_DST_ROI_SIZE_0 */

#define DMA_CH_0_TDMA_DST_ROI_SIZE_0_VAL_SHIFT                       0

#define DMA_CH_0_TDMA_DST_ROI_SIZE_0_VAL_MASK                        0xFFFFFFFF



/* DMA_CH_0_TDMA_DST_VALID_ELEMENTS_0 */

#define DMA_CH_0_TDMA_DST_VALID_ELEMENTS_0_VAL_SHIFT                 0

#define DMA_CH_0_TDMA_DST_VALID_ELEMENTS_0_VAL_MASK                  0xFFFFFFFF



/* DMA_CH_0_TDMA_DST_START_OFFSET_0 */

#define DMA_CH_0_TDMA_DST_START_OFFSET_0_VAL_SHIFT                   0

#define DMA_CH_0_TDMA_DST_START_OFFSET_0_VAL_MASK                    0xFFFFFFFF



/* DMA_CH_0_TDMA_DST_STRIDE_0 */

#define DMA_CH_0_TDMA_DST_STRIDE_0_VAL_SHIFT                         0

#define DMA_CH_0_TDMA_DST_STRIDE_0_VAL_MASK                          0xFFFFFFFF



/* DMA_CH_0_TDMA_DST_ROI_BASE_1 */

#define DMA_CH_0_TDMA_DST_ROI_BASE_1_VAL_SHIFT                       0

#define DMA_CH_0_TDMA_DST_ROI_BASE_1_VAL_MASK                        0xFFFFFFFF



/* DMA_CH_0_TDMA_DST_ROI_SIZE_1 */

#define DMA_CH_0_TDMA_DST_ROI_SIZE_1_VAL_SHIFT                       0

#define DMA_CH_0_TDMA_DST_ROI_SIZE_1_VAL_MASK                        0xFFFFFFFF



/* DMA_CH_0_TDMA_DST_VALID_ELEMENTS_1 */

#define DMA_CH_0_TDMA_DST_VALID_ELEMENTS_1_VAL_SHIFT                 0

#define DMA_CH_0_TDMA_DST_VALID_ELEMENTS_1_VAL_MASK                  0xFFFFFFFF



/* DMA_CH_0_TDMA_DST_START_OFFSET_1 */

#define DMA_CH_0_TDMA_DST_START_OFFSET_1_VAL_SHIFT                   0

#define DMA_CH_0_TDMA_DST_START_OFFSET_1_VAL_MASK                    0xFFFFFFFF



/* DMA_CH_0_TDMA_DST_STRIDE_1 */

#define DMA_CH_0_TDMA_DST_STRIDE_1_VAL_SHIFT                         0

#define DMA_CH_0_TDMA_DST_STRIDE_1_VAL_MASK                          0xFFFFFFFF



/* DMA_CH_0_TDMA_DST_ROI_BASE_2 */

#define DMA_CH_0_TDMA_DST_ROI_BASE_2_VAL_SHIFT                       0

#define DMA_CH_0_TDMA_DST_ROI_BASE_2_VAL_MASK                        0xFFFFFFFF



/* DMA_CH_0_TDMA_DST_ROI_SIZE_2 */

#define DMA_CH_0_TDMA_DST_ROI_SIZE_2_VAL_SHIFT                       0

#define DMA_CH_0_TDMA_DST_ROI_SIZE_2_VAL_MASK                        0xFFFFFFFF



/* DMA_CH_0_TDMA_DST_VALID_ELEMENTS_2 */

#define DMA_CH_0_TDMA_DST_VALID_ELEMENTS_2_VAL_SHIFT                 0

#define DMA_CH_0_TDMA_DST_VALID_ELEMENTS_2_VAL_MASK                  0xFFFFFFFF



/* DMA_CH_0_TDMA_DST_START_OFFSET_2 */

#define DMA_CH_0_TDMA_DST_START_OFFSET_2_VAL_SHIFT                   0

#define DMA_CH_0_TDMA_DST_START_OFFSET_2_VAL_MASK                    0xFFFFFFFF



/* DMA_CH_0_TDMA_DST_STRIDE_2 */

#define DMA_CH_0_TDMA_DST_STRIDE_2_VAL_SHIFT                         0

#define DMA_CH_0_TDMA_DST_STRIDE_2_VAL_MASK                          0xFFFFFFFF



/* DMA_CH_0_TDMA_DST_ROI_BASE_3 */

#define DMA_CH_0_TDMA_DST_ROI_BASE_3_VAL_SHIFT                       0

#define DMA_CH_0_TDMA_DST_ROI_BASE_3_VAL_MASK                        0xFFFFFFFF



/* DMA_CH_0_TDMA_DST_ROI_SIZE_3 */

#define DMA_CH_0_TDMA_DST_ROI_SIZE_3_VAL_SHIFT                       0

#define DMA_CH_0_TDMA_DST_ROI_SIZE_3_VAL_MASK                        0xFFFFFFFF



/* DMA_CH_0_TDMA_DST_VALID_ELEMENTS_3 */

#define DMA_CH_0_TDMA_DST_VALID_ELEMENTS_3_VAL_SHIFT                 0

#define DMA_CH_0_TDMA_DST_VALID_ELEMENTS_3_VAL_MASK                  0xFFFFFFFF



/* DMA_CH_0_TDMA_DST_START_OFFSET_3 */

#define DMA_CH_0_TDMA_DST_START_OFFSET_3_VAL_SHIFT                   0

#define DMA_CH_0_TDMA_DST_START_OFFSET_3_VAL_MASK                    0xFFFFFFFF



/* DMA_CH_0_TDMA_DST_STRIDE_3 */

#define DMA_CH_0_TDMA_DST_STRIDE_3_VAL_SHIFT                         0

#define DMA_CH_0_TDMA_DST_STRIDE_3_VAL_MASK                          0xFFFFFFFF



/* DMA_CH_0_TDMA_DST_ROI_BASE_4 */

#define DMA_CH_0_TDMA_DST_ROI_BASE_4_VAL_SHIFT                       0

#define DMA_CH_0_TDMA_DST_ROI_BASE_4_VAL_MASK                        0xFFFFFFFF



/* DMA_CH_0_TDMA_DST_ROI_SIZE_4 */

#define DMA_CH_0_TDMA_DST_ROI_SIZE_4_VAL_SHIFT                       0

#define DMA_CH_0_TDMA_DST_ROI_SIZE_4_VAL_MASK                        0xFFFFFFFF



/* DMA_CH_0_TDMA_DST_VALID_ELEMENTS_4 */

#define DMA_CH_0_TDMA_DST_VALID_ELEMENTS_4_VAL_SHIFT                 0

#define DMA_CH_0_TDMA_DST_VALID_ELEMENTS_4_VAL_MASK                  0xFFFFFFFF



/* DMA_CH_0_TDMA_DST_START_OFFSET_4 */

#define DMA_CH_0_TDMA_DST_START_OFFSET_4_VAL_SHIFT                   0

#define DMA_CH_0_TDMA_DST_START_OFFSET_4_VAL_MASK                    0xFFFFFFFF



/* DMA_CH_0_TDMA_DST_STRIDE_4 */

#define DMA_CH_0_TDMA_DST_STRIDE_4_VAL_SHIFT                         0

#define DMA_CH_0_TDMA_DST_STRIDE_4_VAL_MASK                          0xFFFFFFFF



/* DMA_CH_0_MEM_INIT_BUSY */

#define DMA_CH_0_MEM_INIT_BUSY_SBC_DATA_SHIFT                        0

#define DMA_CH_0_MEM_INIT_BUSY_SBC_DATA_MASK                         0xFF

#define DMA_CH_0_MEM_INIT_BUSY_SBC_MD_SHIFT                          8

#define DMA_CH_0_MEM_INIT_BUSY_SBC_MD_MASK                           0x100



#endif /* ASIC_REG_DMA_CH_0_MASKS_H_ */

drivers/misc/habanalabs/include/goya/asic_reg/goya_regs.h

+1 −0
Original line number Diff line number Diff line
@@ -88,6 +88,7 @@ 
#include "psoc_global_conf_masks.h"

#include "dma_macro_masks.h"

#include "dma_qm_0_masks.h"

#include "dma_ch_0_masks.h"

#include "tpc0_qm_masks.h"

#include "tpc0_cmdq_masks.h"

#include "mme_qm_masks.h"

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