Commit ac4c244d authored by Vineet Gupta's avatar Vineet Gupta
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ARC: irqflags - Interrupt enabling/disabling at in-core intc 



ARC700 has an in-core intc which provides 2 priorities (a.k.a.) "levels"
of interrupts (per IRQ) hencforth referred to as L1/L2 interrupts.

CPU flags register STATUS32 has Interrupt Enable bits per level (E1/E2)
to globally enable (or disable) all IRQs at a level. Hence the
implementation of arch_local_irq_{save,restore,enable,disable}( )

The STATUS32 reg can be r/w only using the AUX Interface of ARC, hence
the use of LR/SR instructions. Further, E1/E2 bits in there can only be
updated using the FLAG insn.

The intc supports 32 interrupts - and per IRQ enabling is controlled by
a bit in the AUX_IENABLE register, hence the implmentation of
arch_{,un}mask_irq( ) routines.

Signed-off-by: default avatarVineet Gupta <vgupta@synopsys.com>
Cc: Thomas Gleixner <tglx@linutronix.de>
parent cfdbc2e1

arch/arc/include/asm/arcregs.h

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/*

 * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 as

 * published by the Free Software Foundation.

 */



#ifndef _ASM_ARC_ARCREGS_H

#define _ASM_ARC_ARCREGS_H



#ifdef __KERNEL__



/* status32 Bits Positions */

#define STATUS_H_BIT		0	/* CPU Halted */

#define STATUS_E1_BIT		1	/* Int 1 enable */

#define STATUS_E2_BIT		2	/* Int 2 enable */

#define STATUS_A1_BIT		3	/* Int 1 active */

#define STATUS_A2_BIT		4	/* Int 2 active */

#define STATUS_AE_BIT		5	/* Exception active */

#define STATUS_DE_BIT		6	/* PC is in delay slot */

#define STATUS_U_BIT		7	/* User/Kernel mode */

#define STATUS_L_BIT		12	/* Loop inhibit */



/* These masks correspond to the status word(STATUS_32) bits */

#define STATUS_H_MASK		(1<<STATUS_H_BIT)

#define STATUS_E1_MASK		(1<<STATUS_E1_BIT)

#define STATUS_E2_MASK		(1<<STATUS_E2_BIT)

#define STATUS_A1_MASK		(1<<STATUS_A1_BIT)

#define STATUS_A2_MASK		(1<<STATUS_A2_BIT)

#define STATUS_AE_MASK		(1<<STATUS_AE_BIT)

#define STATUS_DE_MASK		(1<<STATUS_DE_BIT)

#define STATUS_U_MASK		(1<<STATUS_U_BIT)

#define STATUS_L_MASK		(1<<STATUS_L_BIT)



/* Auxiliary registers */

#define AUX_IDENTITY		4

#define AUX_INTR_VEC_BASE	0x25

#define AUX_IRQ_LEV		0x200	/* IRQ Priority: L1 or L2 */

#define AUX_IRQ_HINT		0x201	/* For generating Soft Interrupts */

#define AUX_IRQ_LV12		0x43	/* interrupt level register */



#define AUX_IENABLE		0x40c

#define AUX_ITRIGGER		0x40d

#define AUX_IPULSE		0x415



#ifndef __ASSEMBLY__



/*

 ******************************************************************

 *      Inline ASM macros to read/write AUX Regs

 *      Essentially invocation of lr/sr insns from "C"

 */



#if 1



#define read_aux_reg(reg)	__builtin_arc_lr(reg)



/* gcc builtin sr needs reg param to be long immediate */

#define write_aux_reg(reg_immed, val)		\

		__builtin_arc_sr((unsigned int)val, reg_immed)



#else



#define read_aux_reg(reg)		\

({					\

	unsigned int __ret;		\

	__asm__ __volatile__(		\

	"	lr    %0, [%1]"		\

	: "=r"(__ret)			\

	: "i"(reg));			\

	__ret;				\

})



/*

 * Aux Reg address is specified as long immediate by caller

 * e.g.

 *    write_aux_reg(0x69, some_val);

 * This generates tightest code.

 */

#define write_aux_reg(reg_imm, val)	\

({					\

	__asm__ __volatile__(		\

	"	sr   %0, [%1]	\n"	\

	:				\

	: "ir"(val), "i"(reg_imm));	\

})



/*

 * Aux Reg address is specified in a variable

 *  * e.g.

 *      reg_num = 0x69

 *      write_aux_reg2(reg_num, some_val);

 * This has to generate glue code to load the reg num from

 *  memory to a reg hence not recommended.

 */

#define write_aux_reg2(reg_in_var, val)		\

({						\

	unsigned int tmp;			\

						\

	__asm__ __volatile__(			\

	"	ld   %0, [%2]	\n\t"		\

	"	sr   %1, [%0]	\n\t"		\

	: "=&r"(tmp)				\

	: "r"(val), "memory"(&reg_in_var));	\

})



#endif



#endif /* __ASEMBLY__ */



#endif /* __KERNEL__ */



#endif /* _ASM_ARC_ARCREGS_H */

arch/arc/include/asm/irqflags.h

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/*

 * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 as

 * published by the Free Software Foundation.

 */



#ifndef __ASM_ARC_IRQFLAGS_H

#define __ASM_ARC_IRQFLAGS_H



/* vineetg: March 2010 : local_irq_save( ) optimisation

 *  -Remove explicit mov of current status32 into reg, that is not needed

 *  -Use BIC  insn instead of INVERTED + AND

 *  -Conditionally disable interrupts (if they are not enabled, don't disable)

*/



#ifdef __KERNEL__



#include <asm/arcregs.h>



#ifndef __ASSEMBLY__



/******************************************************************

 * IRQ Control Macros

 ******************************************************************/



/*

 * Save IRQ state and disable IRQs

 */

static inline long arch_local_irq_save(void)

{

	unsigned long temp, flags;



	__asm__ __volatile__(

	"	lr  %1, [status32]	\n"

	"	bic %0, %1, %2		\n"

	"	and.f 0, %1, %2	\n"

	"	flag.nz %0		\n"

	: "=r"(temp), "=r"(flags)

	: "n"((STATUS_E1_MASK | STATUS_E2_MASK))

	: "cc");



	return flags;

}



/*

 * restore saved IRQ state

 */

static inline void arch_local_irq_restore(unsigned long flags)

{



	__asm__ __volatile__(

	"	flag %0			\n"

	:

	: "r"(flags));

}



/*

 * Unconditionally Enable IRQs

 */

extern void arch_local_irq_enable(void);



/*

 * Unconditionally Disable IRQs

 */

static inline void arch_local_irq_disable(void)

{

	unsigned long temp;



	__asm__ __volatile__(

	"	lr  %0, [status32]	\n"

	"	and %0, %0, %1		\n"

	"	flag %0			\n"

	: "=&r"(temp)

	: "n"(~(STATUS_E1_MASK | STATUS_E2_MASK)));

}



/*

 * save IRQ state

 */

static inline long arch_local_save_flags(void)

{

	unsigned long temp;



	__asm__ __volatile__(

	"	lr  %0, [status32]	\n"

	: "=&r"(temp));



	return temp;

}



/*

 * Query IRQ state

 */

static inline int arch_irqs_disabled_flags(unsigned long flags)

{

	return !(flags & (STATUS_E1_MASK));

}



static inline int arch_irqs_disabled(void)

{

	return arch_irqs_disabled_flags(arch_local_save_flags());

}



static inline void arch_mask_irq(unsigned int irq)

{

	unsigned int ienb;



	ienb = read_aux_reg(AUX_IENABLE);

	ienb &= ~(1 << irq);

	write_aux_reg(AUX_IENABLE, ienb);

}



static inline void arch_unmask_irq(unsigned int irq)

{

	unsigned int ienb;



	ienb = read_aux_reg(AUX_IENABLE);

	ienb |= (1 << irq);

	write_aux_reg(AUX_IENABLE, ienb);

}



#else



.macro IRQ_DISABLE  scratch

	lr	\scratch, [status32]

	bic	\scratch, \scratch, (STATUS_E1_MASK | STATUS_E2_MASK)

	flag	\scratch

.endm



.macro IRQ_DISABLE_SAVE  scratch, save

	lr	\scratch, [status32]

	mov	\save, \scratch		/* Make a copy */

	bic	\scratch, \scratch, (STATUS_E1_MASK | STATUS_E2_MASK)

	flag	\scratch

.endm



.macro IRQ_ENABLE  scratch

	lr	\scratch, [status32]

	or	\scratch, \scratch, (STATUS_E1_MASK | STATUS_E2_MASK)

	flag	\scratch

.endm



#endif	/* __ASSEMBLY__ */



#endif	/* KERNEL */



#endif

arch/arc/kernel/irq.c

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/*

 * Copyright (C) 2011-12 Synopsys, Inc. (www.synopsys.com)

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 as

 * published by the Free Software Foundation.

 *

 */



#include <linux/interrupt.h>

#include <linux/module.h>

#include <asm/irqflags.h>

#include <asm/arcregs.h>



void arch_local_irq_enable(void)

{

	unsigned long flags;



	/*

	 * ARC IDE Drivers tries to re-enable interrupts from hard-isr

	 * context which is simply wrong

	 */

	if (in_irq()) {

		WARN_ONCE(1, "IRQ enabled from hard-isr");

		return;

	}



	flags = arch_local_save_flags();

	flags |= (STATUS_E1_MASK | STATUS_E2_MASK);

	arch_local_irq_restore(flags);

}

EXPORT_SYMBOL(arch_local_irq_enable);

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