Commit ac3e0be6 authored by Olof Johansson's avatar Olof Johansson
Browse files

Merge tag 'amlogic-dt-2' of... 

Merge tag 'amlogic-dt-2' of https://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-amlogic into next/dt

ARM: dts: Amlogic updates for v4.21, round 2

Highlights
- add CPU OPP tables
- timers: add global timer and TWD

* tag 'amlogic-dt-2' of https://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-amlogic

:
  ARM: dts: meson: meson8b: add the CPU OPP tables
  ARM: dts: meson: meson8: add the CPU OPP table
  ARM: dts: meson8b: add the Cortex-A5 global timer
  ARM: dts: meson8b: add the ARM TWD timer
  ARM: dts: meson8: add the Cortex-A9 global timer
  ARM: dts: meson8: add the ARM TWD timer
  ARM: dts: meson: group the Cortex-A5 / Cortex-A9 peripherals
  dt-bindings: clock: meson8b: export the CPU post dividers

Signed-off-by: default avatarOlof Johansson <olof@lixom.net>
parents ba97d019 c311552a

arch/arm/boot/dts/meson.dtsi

+16 −8
Original line number Diff line number Diff line
@@ -59,14 +59,6 @@ 
		cache-level = <2>;

	};



	gic: interrupt-controller@c4301000 {

		compatible = "arm,cortex-a9-gic";

		reg = <0xc4301000 0x1000>,

		      <0xc4300100 0x0100>;

		interrupt-controller;

		#interrupt-cells = <3>;

	};



	soc {

		compatible = "simple-bus";

		#address-cells = <1>;
@@ -207,6 +199,22 @@ 
			};

		};



		periph: bus@c4300000 {

			compatible = "simple-bus";

			reg = <0xc4300000 0x10000>;

			#address-cells = <1>;

			#size-cells = <1>;

			ranges = <0x0 0xc4300000 0x10000>;



			gic: interrupt-controller@1000 {

				compatible = "arm,cortex-a9-gic";

				reg = <0x1000 0x1000>,

				      <0x100 0x100>;

				interrupt-controller;

				#interrupt-cells = <3>;

			};

		};



		aobus: aobus@c8100000 {

			compatible = "simple-bus";

			reg = <0xc8100000 0x100000>;

arch/arm/boot/dts/meson8.dtsi

+99 −5
Original line number Diff line number Diff line
@@ -64,6 +64,8 @@ 
			reg = <0x200>;

			enable-method = "amlogic,meson8-smp";

			resets = <&clkc CLKC_RESET_CPU0_SOFT_RESET>;

			operating-points-v2 = <&cpu_opp_table>;

			clocks = <&clkc CLKID_CPUCLK>;

		};



		cpu1: cpu@201 {
@@ -73,6 +75,8 @@ 
			reg = <0x201>;

			enable-method = "amlogic,meson8-smp";

			resets = <&clkc CLKC_RESET_CPU1_SOFT_RESET>;

			operating-points-v2 = <&cpu_opp_table>;

			clocks = <&clkc CLKID_CPUCLK>;

		};



		cpu2: cpu@202 {
@@ -82,6 +86,8 @@ 
			reg = <0x202>;

			enable-method = "amlogic,meson8-smp";

			resets = <&clkc CLKC_RESET_CPU2_SOFT_RESET>;

			operating-points-v2 = <&cpu_opp_table>;

			clocks = <&clkc CLKID_CPUCLK>;

		};



		cpu3: cpu@203 {
@@ -91,6 +97,72 @@ 
			reg = <0x203>;

			enable-method = "amlogic,meson8-smp";

			resets = <&clkc CLKC_RESET_CPU3_SOFT_RESET>;

			operating-points-v2 = <&cpu_opp_table>;

			clocks = <&clkc CLKID_CPUCLK>;

		};

	};



	cpu_opp_table: opp-table {

		compatible = "operating-points-v2";

		opp-shared;



		opp-96000000 {

			opp-hz = /bits/ 64 <96000000>;

			opp-microvolt = <825000>;

		};

		opp-192000000 {

			opp-hz = /bits/ 64 <192000000>;

			opp-microvolt = <825000>;

		};

		opp-312000000 {

			opp-hz = /bits/ 64 <312000000>;

			opp-microvolt = <825000>;

		};

		opp-408000000 {

			opp-hz = /bits/ 64 <408000000>;

			opp-microvolt = <825000>;

		};

		opp-504000000 {

			opp-hz = /bits/ 64 <504000000>;

			opp-microvolt = <825000>;

		};

		opp-600000000 {

			opp-hz = /bits/ 64 <600000000>;

			opp-microvolt = <850000>;

		};

		opp-720000000 {

			opp-hz = /bits/ 64 <720000000>;

			opp-microvolt = <850000>;

		};

		opp-816000000 {

			opp-hz = /bits/ 64 <816000000>;

			opp-microvolt = <875000>;

		};

		opp-1008000000 {

			opp-hz = /bits/ 64 <1008000000>;

			opp-microvolt = <925000>;

		};

		opp-1200000000 {

			opp-hz = /bits/ 64 <1200000000>;

			opp-microvolt = <975000>;

		};

		opp-1416000000 {

			opp-hz = /bits/ 64 <1416000000>;

			opp-microvolt = <1025000>;

		};

		opp-1608000000 {

			opp-hz = /bits/ 64 <1608000000>;

			opp-microvolt = <1100000>;

		};

		opp-1800000000 {

			status = "disabled";

			opp-hz = /bits/ 64 <1800000000>;

			opp-microvolt = <1125000>;

		};

		opp-1992000000 {

			status = "disabled";

			opp-hz = /bits/ 64 <1992000000>;

			opp-microvolt = <1150000>;

		};

	};
@@ -129,11 +201,6 @@ 
			no-map;

		};

	};



	scu@c4300000 {

		compatible = "arm,cortex-a9-scu";

		reg = <0xc4300000 0x100>;

	};

}; /* end of / */



&aobus {
@@ -362,6 +429,33 @@ 
	arm,shared-override;

};



&periph {

	scu@0 {

		compatible = "arm,cortex-a9-scu";

		reg = <0x0 0x100>;

	};



	timer@200 {

		compatible = "arm,cortex-a9-global-timer";

		reg = <0x200 0x20>;

		interrupts = <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>;

		clocks = <&clkc CLKID_PERIPH>;



		/*

		 * the arm_global_timer driver currently does not handle clock

		 * rate changes. Keep it disabled for now.

		 */

		status = "disabled";

	};



	timer@600 {

		compatible = "arm,cortex-a9-twd-timer";

		reg = <0x600 0x20>;

		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>;

		clocks = <&clkc CLKID_PERIPH>;

	};

};



&pwm_ab {

	compatible = "amlogic,meson8-pwm", "amlogic,meson8b-pwm";

};

arch/arm/boot/dts/meson8b.dtsi

+93 −5
Original line number Diff line number Diff line
@@ -62,6 +62,8 @@ 
			reg = <0x200>;

			enable-method = "amlogic,meson8b-smp";

			resets = <&clkc CLKC_RESET_CPU0_SOFT_RESET>;

			operating-points-v2 = <&cpu_opp_table>;

			clocks = <&clkc CLKID_CPUCLK>;

		};



		cpu1: cpu@201 {
@@ -71,6 +73,8 @@ 
			reg = <0x201>;

			enable-method = "amlogic,meson8b-smp";

			resets = <&clkc CLKC_RESET_CPU1_SOFT_RESET>;

			operating-points-v2 = <&cpu_opp_table>;

			clocks = <&clkc CLKID_CPUCLK>;

		};



		cpu2: cpu@202 {
@@ -80,6 +84,8 @@ 
			reg = <0x202>;

			enable-method = "amlogic,meson8b-smp";

			resets = <&clkc CLKC_RESET_CPU2_SOFT_RESET>;

			operating-points-v2 = <&cpu_opp_table>;

			clocks = <&clkc CLKID_CPUCLK>;

		};



		cpu3: cpu@203 {
@@ -89,6 +95,66 @@ 
			reg = <0x203>;

			enable-method = "amlogic,meson8b-smp";

			resets = <&clkc CLKC_RESET_CPU3_SOFT_RESET>;

			operating-points-v2 = <&cpu_opp_table>;

			clocks = <&clkc CLKID_CPUCLK>;

		};

	};



	cpu_opp_table: opp-table {

		compatible = "operating-points-v2";

		opp-shared;



		opp-96000000 {

			opp-hz = /bits/ 64 <96000000>;

			opp-microvolt = <860000>;

		};

		opp-192000000 {

			opp-hz = /bits/ 64 <192000000>;

			opp-microvolt = <860000>;

		};

		opp-312000000 {

			opp-hz = /bits/ 64 <312000000>;

			opp-microvolt = <860000>;

		};

		opp-408000000 {

			opp-hz = /bits/ 64 <408000000>;

			opp-microvolt = <860000>;

		};

		opp-504000000 {

			opp-hz = /bits/ 64 <504000000>;

			opp-microvolt = <860000>;

		};

		opp-600000000 {

			opp-hz = /bits/ 64 <600000000>;

			opp-microvolt = <860000>;

		};

		opp-720000000 {

			opp-hz = /bits/ 64 <720000000>;

			opp-microvolt = <860000>;

		};

		opp-816000000 {

			opp-hz = /bits/ 64 <816000000>;

			opp-microvolt = <900000>;

		};

		opp-1008000000 {

			opp-hz = /bits/ 64 <1008000000>;

			opp-microvolt = <1140000>;

		};

		opp-1200000000 {

			opp-hz = /bits/ 64 <1200000000>;

			opp-microvolt = <1140000>;

		};

		opp-1320000000 {

			opp-hz = /bits/ 64 <1320000000>;

			opp-microvolt = <1140000>;

		};

		opp-1488000000 {

			opp-hz = /bits/ 64 <1488000000>;

			opp-microvolt = <1140000>;

		};

		opp-1536000000 {

			opp-hz = /bits/ 64 <1536000000>;

			opp-microvolt = <1140000>;

		};

	};
@@ -112,11 +178,6 @@ 
			no-map;

		};

	};



	scu@c4300000 {

		compatible = "arm,cortex-a5-scu";

		reg = <0xc4300000 0x100>;

	};

}; /* end of / */



&aobus {
@@ -349,6 +410,33 @@ 
	arm,shared-override;

};



&periph {

	scu@0 {

		compatible = "arm,cortex-a5-scu";

		reg = <0x0 0x100>;

	};



	timer@200 {

		compatible = "arm,cortex-a5-global-timer";

		reg = <0x200 0x20>;

		interrupts = <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>;

		clocks = <&clkc CLKID_PERIPH>;



		/*

		 * the arm_global_timer driver currently does not handle clock

		 * rate changes. Keep it disabled for now.

		 */

		status = "disabled";

	};



	timer@600 {

		compatible = "arm,cortex-a5-twd-timer";

		reg = <0x600 0x20>;

		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>;

		clocks = <&clkc CLKID_PERIPH>;

	};

};



&pwm_ab {

	compatible = "amlogic,meson8b-pwm";

};

include/dt-bindings/clock/meson8b-clkc.h

+4 −0
Original line number Diff line number Diff line
@@ -103,5 +103,9 @@ 
#define CLKID_MPLL1		94

#define CLKID_MPLL2		95

#define CLKID_NAND_CLK		112

#define CLKID_ABP		124

#define CLKID_PERIPH		126

#define CLKID_AXI		128

#define CLKID_L2_DRAM		130



#endif /* __MESON8B_CLKC_H */

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