Commit ac3c1c4f authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge branch 'timers-core-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip 

Pull timer changes from Ingo Molnar:
 "Various clocksource driver updates: extend the core with memory mapped
  hardware (mmio) support and add new (ARM) Moxart SoC and sun4i
  hardware support"

* 'timers-core-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: (23 commits)
  clocksource: arch_timer: Add support for memory mapped timers
  clocksource: arch_timer: Push the read/write wrappers deeper
  Documentation: Add memory mapped ARM architected timer binding
  clocksource: arch_timer: Pass clock event to set_mode callback
  clocksource: arch_timer: Make register accessors less error-prone
  ARM: clocksource: moxart: documentation: Update device tree bindings document
  ARM: clocksource: moxart: Add bitops.h include
  ARM: clocksource: moxart: documentation: Fix device tree bindings document
  ARM: clocksource: Add support for MOXA ART SoCs
  clocksource: cadence_ttc: Reuse clocksource as sched_clock
  clocksource: cadence_ttc: Remove unused header
  clocksource: sun4i: Fix bug when switching from periodic to oneshot modes
  clocksource: sun4i: Cleanup parent clock setup
  clocksource: sun4i: Remove TIMER_SCAL variable
  clocksource: sun4i: Factor out some timer code
  clocksource: sun4i: Fix the next event code
  clocksource: sun4i: Don't forget to enable the clock we use
  clocksource: sun4i: Add clocksource and sched clock drivers
  clocksource: sun4i: rename AUTORELOAD define to RELOAD
  clocksource: sun4i: Wrap macros arguments in parenthesis
  ...
parents 5e0b3a4e cfb6d656

Documentation/devicetree/bindings/arm/arch_timer.txt

+56 −3
Original line number Diff line number Diff line 
* ARM architected timer



ARM cores may have a per-core architected timer, which provides per-cpu timers.

ARM cores may have a per-core architected timer, which provides per-cpu timers,

or a memory mapped architected timer, which provides up to 8 frames with a

physical and optional virtual timer per frame.



The timer is attached to a GIC to deliver its per-processor interrupts.

The per-core architected timer is attached to a GIC to deliver its

per-processor interrupts via PPIs. The memory mapped timer is attached to a GIC

to deliver its interrupts via SPIs.



** Timer node properties:

** CP15 Timer node properties:



- compatible : Should at least contain one of

	"arm,armv7-timer"
@@ -26,3 +30,52 @@ Example: 
			     <1 10 0xf08>;

		clock-frequency = <100000000>;

	};



** Memory mapped timer node properties:



- compatible : Should at least contain "arm,armv7-timer-mem".



- clock-frequency : The frequency of the main counter, in Hz. Optional.



- reg : The control frame base address.



Note that #address-cells, #size-cells, and ranges shall be present to ensure

the CPU can address a frame's registers.



A timer node has up to 8 frame sub-nodes, each with the following properties:



- frame-number: 0 to 7.



- interrupts : Interrupt list for physical and virtual timers in that order.

  The virtual timer interrupt is optional.



- reg : The first and second view base addresses in that order. The second view

  base address is optional.



- status : "disabled" indicates the frame is not available for use. Optional.



Example:



	timer@f0000000 {

		compatible = "arm,armv7-timer-mem";

		#address-cells = <1>;

		#size-cells = <1>;

		ranges;

		reg = <0xf0000000 0x1000>;

		clock-frequency = <50000000>;



		frame@f0001000 {

			frame-number = <0>

			interrupts = <0 13 0x8>,

				     <0 14 0x8>;

			reg = <0xf0001000 0x1000>,

			      <0xf0002000 0x1000>;

		};



		frame@f0003000 {

			frame-number = <1>

			interrupts = <0 15 0x8>;

			reg = <0xf0003000 0x1000>;

			status = "disabled";

		};

	};

Documentation/devicetree/bindings/timer/moxa,moxart-timer.txt

0 → 100644
+17 −0
Original line number Diff line number Diff line 
MOXA ART timer



Required properties:



- compatible : Must be "moxa,moxart-timer"

- reg : Should contain registers location and length

- interrupts : Should contain the timer interrupt number

- clocks : Should contain phandle for the clock that drives the counter



Example:



	timer: timer@98400000 {

		compatible = "moxa,moxart-timer";

		reg = <0x98400000 0x42>;

		interrupts = <19 1>;

		clocks = <&coreclk>;

	};

MAINTAINERS

+8 −2
Original line number Diff line number Diff line
@@ -2125,6 +2125,13 @@ M: Russell King <linux@arm.linux.org.uk> 
S:	Maintained

F:	include/linux/clk.h



CLOCKSOURCE, CLOCKEVENT DRIVERS

M:	Daniel Lezcano <daniel.lezcano@linaro.org>

M:	Thomas Gleixner <tglx@linutronix.de>

T:	git git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip.git timers/core

S:	Supported

F:	drivers/clocksource



CISCO FCOE HBA DRIVER

M:	Hiral Patel <hiralpat@cisco.com>

M:	Suma Ramars <sramars@cisco.com>
@@ -7156,7 +7163,7 @@ S: Maintained 
F:	include/linux/mmc/dw_mmc.h

F:	drivers/mmc/host/dw_mmc*



TIMEKEEPING, NTP

TIMEKEEPING, CLOCKSOURCE CORE, NTP

M:	John Stultz <john.stultz@linaro.org>

M:	Thomas Gleixner <tglx@linutronix.de>

T:	git git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip.git timers/core
@@ -7169,7 +7176,6 @@ F: include/uapi/linux/timex.h 
F:	kernel/time/clocksource.c

F:	kernel/time/time*.c

F:	kernel/time/ntp.c

F:	drivers/clocksource



TLG2300 VIDEO4LINUX-2 DRIVER

M:	Huang Shijie <shijie8@gmail.com>

arch/arm/include/asm/arch_timer.h

+6 −8
Original line number Diff line number Diff line
@@ -17,7 +17,8 @@ int arch_timer_arch_init(void); 
 * nicely work out which register we want, and chuck away the rest of

 * the code. At least it does so with a recent GCC (4.6.3).

 */

static inline void arch_timer_reg_write(const int access, const int reg, u32 val)

static __always_inline

void arch_timer_reg_write_cp15(int access, enum arch_timer_reg reg, u32 val)

{

	if (access == ARCH_TIMER_PHYS_ACCESS) {

		switch (reg) {
@@ -28,9 +29,7 @@ static inline void arch_timer_reg_write(const int access, const int reg, u32 val 
			asm volatile("mcr p15, 0, %0, c14, c2, 0" : : "r" (val));

			break;

		}

	}



	if (access == ARCH_TIMER_VIRT_ACCESS) {

	} else if (access == ARCH_TIMER_VIRT_ACCESS) {

		switch (reg) {

		case ARCH_TIMER_REG_CTRL:

			asm volatile("mcr p15, 0, %0, c14, c3, 1" : : "r" (val));
@@ -44,7 +43,8 @@ static inline void arch_timer_reg_write(const int access, const int reg, u32 val 
	isb();

}



static inline u32 arch_timer_reg_read(const int access, const int reg)

static __always_inline

u32 arch_timer_reg_read_cp15(int access, enum arch_timer_reg reg)

{

	u32 val = 0;
@@ -57,9 +57,7 @@ static inline u32 arch_timer_reg_read(const int access, const int reg) 
			asm volatile("mrc p15, 0, %0, c14, c2, 0" : "=r" (val));

			break;

		}

	}



	if (access == ARCH_TIMER_VIRT_ACCESS) {

	} else if (access == ARCH_TIMER_VIRT_ACCESS) {

		switch (reg) {

		case ARCH_TIMER_REG_CTRL:

			asm volatile("mrc p15, 0, %0, c14, c3, 1" : "=r" (val));

arch/arm64/include/asm/arch_timer.h

+9 −14
Original line number Diff line number Diff line
@@ -26,7 +26,13 @@ 


#include <clocksource/arm_arch_timer.h>



static inline void arch_timer_reg_write(int access, int reg, u32 val)

/*

 * These register accessors are marked inline so the compiler can

 * nicely work out which register we want, and chuck away the rest of

 * the code.

 */

static __always_inline

void arch_timer_reg_write_cp15(int access, enum arch_timer_reg reg, u32 val)

{

	if (access == ARCH_TIMER_PHYS_ACCESS) {

		switch (reg) {
@@ -36,8 +42,6 @@ static inline void arch_timer_reg_write(int access, int reg, u32 val) 
		case ARCH_TIMER_REG_TVAL:

			asm volatile("msr cntp_tval_el0, %0" : : "r" (val));

			break;

		default:

			BUILD_BUG();

		}

	} else if (access == ARCH_TIMER_VIRT_ACCESS) {

		switch (reg) {
@@ -47,17 +51,14 @@ static inline void arch_timer_reg_write(int access, int reg, u32 val) 
		case ARCH_TIMER_REG_TVAL:

			asm volatile("msr cntv_tval_el0, %0" : : "r" (val));

			break;

		default:

			BUILD_BUG();

		}

	} else {

		BUILD_BUG();

	}



	isb();

}



static inline u32 arch_timer_reg_read(int access, int reg)

static __always_inline

u32 arch_timer_reg_read_cp15(int access, enum arch_timer_reg reg)

{

	u32 val;
@@ -69,8 +70,6 @@ static inline u32 arch_timer_reg_read(int access, int reg) 
		case ARCH_TIMER_REG_TVAL:

			asm volatile("mrs %0, cntp_tval_el0" : "=r" (val));

			break;

		default:

			BUILD_BUG();

		}

	} else if (access == ARCH_TIMER_VIRT_ACCESS) {

		switch (reg) {
@@ -80,11 +79,7 @@ static inline u32 arch_timer_reg_read(int access, int reg) 
		case ARCH_TIMER_REG_TVAL:

			asm volatile("mrs %0, cntv_tval_el0" : "=r" (val));

			break;

		default:

			BUILD_BUG();

		}

	} else {

		BUILD_BUG();

	}



	return val;

CRA Git | Maintained and supported by SUSTech CRA and CCSE