ARM: dts: rockchip: convert rk3188 to opp-v2

			compatible = "arm,cortex-a9";

			next-level-cache = <&L2>;

			reg = <0x0>;

			operating-points = <

				/* kHz    uV */

				1608000 1350000

				1416000 1250000

				1200000 1150000

				1008000 1075000

				 816000  975000

				 600000  950000

				 504000  925000

				 312000  875000

			>;

			clock-latency = <40000>;

			clocks = <&cru ARMCLK>;

			operating-points-v2 = <&cpu0_opp_table>;

		};

		cpu@1 {

			device_type = "cpu";

			compatible = "arm,cortex-a9";

			next-level-cache = <&L2>;

			reg = <0x1>;

			operating-points-v2 = <&cpu0_opp_table>;

		};

		cpu@2 {

			device_type = "cpu";

			compatible = "arm,cortex-a9";

			next-level-cache = <&L2>;

			reg = <0x2>;

			operating-points-v2 = <&cpu0_opp_table>;

		};

		cpu@3 {

			device_type = "cpu";

			compatible = "arm,cortex-a9";

			next-level-cache = <&L2>;

			reg = <0x3>;

			operating-points-v2 = <&cpu0_opp_table>;

		};

	};

	cpu0_opp_table: opp_table0 {

		compatible = "operating-points-v2";

		opp-shared;

		opp-312000000 {

			opp-hz = /bits/ 64 <312000000>;

			opp-microvolt = <875000>;

			clock-latency-ns = <40000>;

		};

		opp-504000000 {

			opp-hz = /bits/ 64 <504000000>;

			opp-microvolt = <925000>;

		};

		opp-600000000 {

			opp-hz = /bits/ 64 <600000000>;

			opp-microvolt = <950000>;

			opp-suspend;

		};

		opp-816000000 {

			opp-hz = /bits/ 64 <816000000>;

			opp-microvolt = <975000>;

		};

		opp-1008000000 {

			opp-hz = /bits/ 64 <1008000000>;

			opp-microvolt = <1075000>;

		};

		opp-1200000000 {

			opp-hz = /bits/ 64 <1200000000>;

			opp-microvolt = <1150000>;

		};

		opp-1416000000 {

			opp-hz = /bits/ 64 <1416000000>;

			opp-microvolt = <1250000>;

		};

		opp-1608000000 {

			opp-hz = /bits/ 64 <1608000000>;

			opp-microvolt = <1350000>;

		};

	};