Commit abb90a24 authored by Greentime Hu's avatar Greentime Hu
Browse files

nds32: To fix a cache inconsistency issue by setting correct cacheability of NTC 



The nds32 architecture will use physical memory when interrupt or
exception comes and it will use the setting of NTC0-4. The original
implementation didn't consider the DRAM start address may start from 1GB,
2GB or 3GB to cause this issue. It will write the data to DRAM if it is
running in physical address however kernel will read the data with
virtaul address through data cache. In this case, the data of DRAM is
latest.

This fix will set the correct cacheability to let kernel write/read the
latest data in cache instead of DRAM.

Signed-off-by: default avatarGreentime Hu <greentime@andestech.com>
parent 8769c223

arch/nds32/include/asm/bitfield.h

+1 −0
Original line number Diff line number Diff line
@@ -396,6 +396,7 @@ 
#define MMU_CTL_D8KB		1

#define MMU_CTL_UNA		( 0x1  << MMU_CTL_offUNA )



#define MMU_CTL_CACHEABLE_NON   0

#define MMU_CTL_CACHEABLE_WB	2

#define MMU_CTL_CACHEABLE_WT	3

arch/nds32/kernel/head.S

+23 −5
Original line number Diff line number Diff line
@@ -57,14 +57,32 @@ _nodtb: 
	isb

	mtsr    $r4, $L1_PPTB       ! load page table pointer\n"



/* set NTC0 cacheable/writeback, mutliple page size in use */

#ifdef CONFIG_CPU_DCACHE_DISABLE

	#define MMU_CTL_NTCC MMU_CTL_CACHEABLE_NON

#else

	#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH

		#define MMU_CTL_NTCC MMU_CTL_CACHEABLE_WT

	#else

		#define MMU_CTL_NTCC MMU_CTL_CACHEABLE_WB

	#endif

#endif



/* set NTC cacheability, mutliple page size in use */

	mfsr    $r3, $MMU_CTL

	li      $r0, #~MMU_CTL_mskNTC0

	and     $r3, $r3, $r0

#if CONFIG_MEMORY_START >= 0xc0000000

	ori     $r3, $r3, (MMU_CTL_NTCC << MMU_CTL_offNTC3)

#elif CONFIG_MEMORY_START >= 0x80000000

	ori     $r3, $r3, (MMU_CTL_NTCC << MMU_CTL_offNTC2)

#elif CONFIG_MEMORY_START >= 0x40000000

	ori     $r3, $r3, (MMU_CTL_NTCC << MMU_CTL_offNTC1)

#else

	ori     $r3, $r3, (MMU_CTL_NTCC << MMU_CTL_offNTC0)

#endif



#ifdef CONFIG_ANDES_PAGE_SIZE_4KB

	ori     $r3, $r3, #(MMU_CTL_mskMPZIU|(MMU_CTL_CACHEABLE_WB << MMU_CTL_offNTC0))

	ori     $r3, $r3, #(MMU_CTL_mskMPZIU)

#else

	ori     $r3, $r3, #(MMU_CTL_mskMPZIU|(MMU_CTL_CACHEABLE_WB << MMU_CTL_offNTC0)|MMU_CTL_D8KB)

	ori     $r3, $r3, #(MMU_CTL_mskMPZIU|MMU_CTL_D8KB)

#endif

#ifdef CONFIG_HW_SUPPORT_UNALIGNMENT_ACCESS

	li      $r0, #MMU_CTL_UNA

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