drm/amdgpu/virt: implement VI virt operation interfaces (ab71ac56) · Commits · 戴 / test

drivers/gpu/drm/amd/amdgpu/Makefile

+1 −1

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		@@ -34,7 +34,7 @@ amdgpu-$(CONFIG_DRM_AMDGPU_CIK)+= cik.o cik_ih.o kv_smc.o kv_dpm.o \
		amdgpu-$(CONFIG_DRM_AMDGPU_SI)+= si.o gmc_v6_0.o gfx_v6_0.o si_ih.o si_dma.o dce_v6_0.o si_dpm.o si_smc.o

		amdgpu-y += \
		vi.o
		vi.o mxgpu_vi.o

		# add GMC block
		amdgpu-y += \

drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h

+3 −0

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		@@ -46,6 +46,9 @@ struct amdgpu_virt {
		uint64_t csa_vmid0_addr;
		uint32_t reg_val_offs;
		struct mutex lock;
		struct amdgpu_irq_src ack_irq;
		struct amdgpu_irq_src rcv_irq;
		struct delayed_work flr_work;
		const struct amdgpu_virt_ops *ops;
		};

drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c

0 → 100644

+592 −0

File added.

Preview size limit exceeded, changes collapsed.

drivers/gpu/drm/amd/amdgpu/mxgpu_vi.h

0 → 100644

+55 −0

Original line number	Diff line number	Diff line
		/*
		* Copyright 2017 Advanced Micro Devices, Inc.
		*
		* Permission is hereby granted, free of charge, to any person obtaining a
		* copy of this software and associated documentation files (the "Software"),
		* to deal in the Software without restriction, including without limitation
		* the rights to use, copy, modify, merge, publish, distribute, sublicense,
		* and/or sell copies of the Software, and to permit persons to whom the
		* Software is furnished to do so, subject to the following conditions:
		*
		* The above copyright notice and this permission notice shall be included in
		* all copies or substantial portions of the Software.
		*
		* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
		* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
		* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
		* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
		* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
		* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
		* OTHER DEALINGS IN THE SOFTWARE.
		*/

		#ifndef __MXGPU_VI_H__
		#define __MXGPU_VI_H__

		#define VI_MAILBOX_TIMEDOUT 150
		#define VI_MAILBOX_RESET_TIME 12

		/* VI mailbox messages request */
		enum idh_request {
		IDH_REQ_GPU_INIT_ACCESS = 1,
		IDH_REL_GPU_INIT_ACCESS,
		IDH_REQ_GPU_FINI_ACCESS,
		IDH_REL_GPU_FINI_ACCESS,
		IDH_REQ_GPU_RESET_ACCESS
		};

		/* VI mailbox messages data */
		enum idh_event {
		IDH_CLR_MSG_BUF = 0,
		IDH_READY_TO_ACCESS_GPU,
		IDH_FLR_NOTIFICATION,
		IDH_FLR_NOTIFICATION_CMPL,
		IDH_EVENT_MAX
		};

		extern const struct amdgpu_virt_ops xgpu_vi_virt_ops;

		void xgpu_vi_init_golden_registers(struct amdgpu_device *adev);
		void xgpu_vi_mailbox_set_irq_funcs(struct amdgpu_device *adev);
		int xgpu_vi_mailbox_add_irq_id(struct amdgpu_device *adev);
		int xgpu_vi_mailbox_get_irq(struct amdgpu_device *adev);
		void xgpu_vi_mailbox_put_irq(struct amdgpu_device *adev);

		#endif

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