clk: sunxi: Add H3 clocks support (ab6e23a4) · Commits · 戴 / test

Documentation/devicetree/bindings/clock/sunxi.txt

+2 −0

Original line number	Diff line number	Diff line
		@@ -29,6 +29,7 @@ Required properties:
		"allwinner,sun6i-a31-ar100-clk" - for the AR100 on A31
		"allwinner,sun9i-a80-cpus-clk" - for the CPUS on A80
		"allwinner,sun6i-a31-ahb1-clk" - for the AHB1 clock on A31
		"allwinner,sun8i-h3-ahb2-clk" - for the AHB2 clock on H3
		"allwinner,sun6i-a31-ahb1-gates-clk" - for the AHB1 gates on A31
		"allwinner,sun8i-a23-ahb1-gates-clk" - for the AHB1 gates on A23
		"allwinner,sun9i-a80-ahb0-gates-clk" - for the AHB0 gates on A80
		@@ -56,6 +57,7 @@ Required properties:
		"allwinner,sun9i-a80-apb1-gates-clk" - for the APB1 gates on A80
		"allwinner,sun6i-a31-apb2-gates-clk" - for the APB2 gates on A31
		"allwinner,sun8i-a23-apb2-gates-clk" - for the APB2 gates on A23
		"allwinner,sun8i-h3-bus-gates-clk" - for the bus gates on H3
		"allwinner,sun9i-a80-apbs-gates-clk" - for the APBS gates on A80
		"allwinner,sun4i-a10-dram-gates-clk" - for the DRAM gates on A10
		"allwinner,sun5i-a13-mbus-clk" - for the MBUS clock on A13

drivers/clk/sunxi/Makefile

+1 −0

Original line number	Diff line number	Diff line
		@@ -10,6 +10,7 @@ obj-y += clk-a10-pll2.o
		obj-y += clk-a20-gmac.o
		obj-y += clk-mod0.o
		obj-y += clk-simple-gates.o
		obj-y += clk-sun8i-bus-gates.o
		obj-y += clk-sun8i-mbus.o
		obj-y += clk-sun9i-core.o
		obj-y += clk-sun9i-mmc.o

drivers/clk/sunxi/clk-sun8i-bus-gates.c

0 → 100644

+112 −0

Original line number	Diff line number	Diff line
		/*
		* Copyright (C) 2015 Jens Kuske <jenskuske@gmail.com>
		*
		* Based on clk-simple-gates.c, which is:
		* Copyright 2015 Maxime Ripard
		*
		* Maxime Ripard <maxime.ripard@free-electrons.com>
		*
		* This program is free software; you can redistribute it and/or modify
		* it under the terms of the GNU General Public License as published by
		* the Free Software Foundation; either version 2 of the License, or
		* (at your option) any later version.
		*
		* This program is distributed in the hope that it will be useful,
		* but WITHOUT ANY WARRANTY; without even the implied warranty of
		* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
		* GNU General Public License for more details.
		*/

		#include <linux/clk.h>
		#include <linux/clk-provider.h>
		#include <linux/of.h>
		#include <linux/of_address.h>
		#include <linux/slab.h>
		#include <linux/spinlock.h>

		static DEFINE_SPINLOCK(gates_lock);

		static void __init sun8i_h3_bus_gates_init(struct device_node *node)
		{
		static const char * const names[] = { "ahb1", "ahb2", "apb1", "apb2" };
		enum { AHB1, AHB2, APB1, APB2, PARENT_MAX } clk_parent;
		const char *parents[PARENT_MAX];
		struct clk_onecell_data *clk_data;
		const char *clk_name;
		struct property *prop;
		struct resource res;
		void __iomem *clk_reg;
		void __iomem *reg;
		const __be32 *p;
		int number, i;
		u8 clk_bit;
		u32 index;

		reg = of_io_request_and_map(node, 0, of_node_full_name(node));
		if (IS_ERR(reg))
		return;

		for (i = 0; i < ARRAY_SIZE(names); i++) {
		index = of_property_match_string(node, "clock-names",
		names[i]);
		if (index < 0)
		return;

		parents[i] = of_clk_get_parent_name(node, index);
		}

		clk_data = kmalloc(sizeof(struct clk_onecell_data), GFP_KERNEL);
		if (!clk_data)
		goto err_unmap;

		number = of_property_count_u32_elems(node, "clock-indices");
		of_property_read_u32_index(node, "clock-indices", number - 1, &number);

		clk_data->clks = kcalloc(number + 1, sizeof(struct clk *), GFP_KERNEL);
		if (!clk_data->clks)
		goto err_free_data;

		i = 0;
		of_property_for_each_u32(node, "clock-indices", prop, p, index) {
		of_property_read_string_index(node, "clock-output-names",
		i, &clk_name);

		if (index == 17 \|\| (index >= 29 && index <= 31))
		clk_parent = AHB2;
		else if (index <= 63 \|\| index >= 128)
		clk_parent = AHB1;
		else if (index >= 64 && index <= 95)
		clk_parent = APB1;
		else if (index >= 96 && index <= 127)
		clk_parent = APB2;

		clk_reg = reg + 4 * (index / 32);
		clk_bit = index % 32;

		clk_data->clks[index] = clk_register_gate(NULL, clk_name,
		parents[clk_parent],
		0, clk_reg, clk_bit,
		0, &gates_lock);
		i++;

		if (IS_ERR(clk_data->clks[index])) {
		WARN_ON(true);
		continue;
		}
		}

		clk_data->clk_num = number + 1;
		of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);

		return;

		err_free_data:
		kfree(clk_data);
		err_unmap:
		iounmap(reg);
		of_address_to_resource(node, 0, &res);
		release_mem_region(res.start, resource_size(&res));
		}

		CLK_OF_DECLARE(sun8i_h3_bus_gates, "allwinner,sun8i-h3-bus-gates-clk",
		sun8i_h3_bus_gates_init);

drivers/clk/sunxi/clk-sunxi.c

+6 −0

Original line number	Diff line number	Diff line
		@@ -778,6 +778,10 @@ static const struct mux_data sun6i_a31_ahb1_mux_data __initconst = {
		.shift = 12,
		};

		static const struct mux_data sun8i_h3_ahb2_mux_data __initconst = {
		.shift = 0,
		};

		static void __init sunxi_mux_clk_setup(struct device_node *node,
		struct mux_data *data)
		{
		@@ -1130,6 +1134,7 @@ static const struct of_device_id clk_divs_match[] __initconst = {
		static const struct of_device_id clk_mux_match[] __initconst = {
		{.compatible = "allwinner,sun4i-a10-cpu-clk", .data = &sun4i_cpu_mux_data,},
		{.compatible = "allwinner,sun6i-a31-ahb1-mux-clk", .data = &sun6i_a31_ahb1_mux_data,},
		{.compatible = "allwinner,sun8i-h3-ahb2-clk", .data = &sun8i_h3_ahb2_mux_data,},
		{}
		};

		@@ -1212,6 +1217,7 @@ CLK_OF_DECLARE(sun6i_a31_clk_init, "allwinner,sun6i-a31", sun6i_init_clocks);
		CLK_OF_DECLARE(sun6i_a31s_clk_init, "allwinner,sun6i-a31s", sun6i_init_clocks);
		CLK_OF_DECLARE(sun8i_a23_clk_init, "allwinner,sun8i-a23", sun6i_init_clocks);
		CLK_OF_DECLARE(sun8i_a33_clk_init, "allwinner,sun8i-a33", sun6i_init_clocks);
		CLK_OF_DECLARE(sun8i_h3_clk_init, "allwinner,sun8i-h3", sun6i_init_clocks);

		static void __init sun9i_init_clocks(struct device_node *node)
		{

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