Commit ab67badd authored by Gal Pressman's avatar Gal Pressman Committed by Jason Gunthorpe
Browse files

RDMA/efa: Be consistent with modify QP bitmask 

The modify QP bitmask was not consistent with other bitmasks used in the
device interface. Remove the bitmask enum and allow usage with
EFA_GET/SET.

Link: https://lore.kernel.org/r/20200731060420.17053-3-galpress@amazon.com


Reviewed-by: default avatarFiras JahJah <firasj@amazon.com>
Reviewed-by: default avatarYossi Leybovich <sleybo@amazon.com>
Signed-off-by: default avatarGal Pressman <galpress@amazon.com>
Signed-off-by: default avatarJason Gunthorpe <jgg@nvidia.com>
parent 34eb009f

drivers/infiniband/hw/efa/efa_admin_cmds_defs.h

+14 −10
Original line number Diff line number Diff line
@@ -68,14 +68,6 @@ enum efa_admin_get_stats_scope { 
	EFA_ADMIN_GET_STATS_SCOPE_QUEUE             = 1,

};



enum efa_admin_modify_qp_mask_bits {

	EFA_ADMIN_QP_STATE_BIT                      = 0,

	EFA_ADMIN_CUR_QP_STATE_BIT                  = 1,

	EFA_ADMIN_QKEY_BIT                          = 2,

	EFA_ADMIN_SQ_PSN_BIT                        = 3,

	EFA_ADMIN_SQ_DRAINED_ASYNC_NOTIFY_BIT       = 4,

};



/*

 * QP allocation sizes, converted by fabric QueuePair (QP) create command

 * from QP capabilities.
@@ -199,8 +191,13 @@ struct efa_admin_modify_qp_cmd { 
	struct efa_admin_aq_common_desc aq_common_desc;



	/*

	 * Mask indicating which fields should be updated see enum

	 * efa_admin_modify_qp_mask_bits

	 * Mask indicating which fields should be updated

	 * 0 : qp_state

	 * 1 : cur_qp_state

	 * 2 : qkey

	 * 3 : sq_psn

	 * 4 : sq_drained_async_notify

	 * 31:5 : reserved

	 */

	u32 modify_mask;
@@ -862,6 +859,13 @@ struct efa_admin_host_info { 
#define EFA_ADMIN_CREATE_QP_CMD_SQ_VIRT_MASK                BIT(0)

#define EFA_ADMIN_CREATE_QP_CMD_RQ_VIRT_MASK                BIT(1)



/* modify_qp_cmd */

#define EFA_ADMIN_MODIFY_QP_CMD_QP_STATE_MASK               BIT(0)

#define EFA_ADMIN_MODIFY_QP_CMD_CUR_QP_STATE_MASK           BIT(1)

#define EFA_ADMIN_MODIFY_QP_CMD_QKEY_MASK                   BIT(2)

#define EFA_ADMIN_MODIFY_QP_CMD_SQ_PSN_MASK                 BIT(3)

#define EFA_ADMIN_MODIFY_QP_CMD_SQ_DRAINED_ASYNC_NOTIFY_MASK BIT(4)



/* reg_mr_cmd */

#define EFA_ADMIN_REG_MR_CMD_PHYS_PAGE_SIZE_SHIFT_MASK      GENMASK(4, 0)

#define EFA_ADMIN_REG_MR_CMD_MEM_ADDR_PHY_MODE_EN_MASK      BIT(7)

drivers/infiniband/hw/efa/efa_verbs.c

+8 −6
Original line number Diff line number Diff line
@@ -804,25 +804,27 @@ int efa_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr, 
	params.qp_handle = qp->qp_handle;



	if (qp_attr_mask & IB_QP_STATE) {

		params.modify_mask |= BIT(EFA_ADMIN_QP_STATE_BIT) |

				      BIT(EFA_ADMIN_CUR_QP_STATE_BIT);

		EFA_SET(&params.modify_mask, EFA_ADMIN_MODIFY_QP_CMD_QP_STATE,

			1);

		EFA_SET(&params.modify_mask,

			EFA_ADMIN_MODIFY_QP_CMD_CUR_QP_STATE, 1);

		params.cur_qp_state = qp_attr->cur_qp_state;

		params.qp_state = qp_attr->qp_state;

	}



	if (qp_attr_mask & IB_QP_EN_SQD_ASYNC_NOTIFY) {

		params.modify_mask |=

			BIT(EFA_ADMIN_SQ_DRAINED_ASYNC_NOTIFY_BIT);

		EFA_SET(&params.modify_mask,

			EFA_ADMIN_MODIFY_QP_CMD_SQ_DRAINED_ASYNC_NOTIFY, 1);

		params.sq_drained_async_notify = qp_attr->en_sqd_async_notify;

	}



	if (qp_attr_mask & IB_QP_QKEY) {

		params.modify_mask |= BIT(EFA_ADMIN_QKEY_BIT);

		EFA_SET(&params.modify_mask, EFA_ADMIN_MODIFY_QP_CMD_QKEY, 1);

		params.qkey = qp_attr->qkey;

	}



	if (qp_attr_mask & IB_QP_SQ_PSN) {

		params.modify_mask |= BIT(EFA_ADMIN_SQ_PSN_BIT);

		EFA_SET(&params.modify_mask, EFA_ADMIN_MODIFY_QP_CMD_SQ_PSN, 1);

		params.sq_psn = qp_attr->sq_psn;

	}

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