Commit ab64920c authored by Arnd Bergmann's avatar Arnd Bergmann
Browse files

Merge tag 'mvebu-soc-suspend-3.19' of git://git.infradead.org/linux-mvebu into next/soc 

Pull "mvebu SoC suspend changes for v3.19" from Jason Cooper:

 - Armada 370/XP suspend/resume support

 - mvebu SoC driver suspend/resume support
    - irqchip
    - clocksource
    - mbus
    - clk

* tag 'mvebu-soc-suspend-3.19' of git://git.infradead.org/linux-mvebu

:
  ARM: mvebu: add SDRAM controller description for Armada XP
  ARM: mvebu: adjust mbus controller description on Armada 370/XP
  ARM: mvebu: add suspend/resume DT information for Armada XP GP
  ARM: mvebu: synchronize secondary CPU clocks on resume
  ARM: mvebu: make sure MMU is disabled in armada_370_xp_cpu_resume
  ARM: mvebu: Armada XP GP specific suspend/resume code
  ARM: mvebu: reserve the first 10 KB of each memory bank for suspend/resume
  ARM: mvebu: implement suspend/resume support for Armada XP
  clk: mvebu: add suspend/resume for gatable clocks
  bus: mvebu-mbus: provide a mechanism to save SDRAM window configuration
  bus: mvebu-mbus: suspend/resume support
  clocksource: time-armada-370-xp: add suspend/resume support
  irqchip: armada-370-xp: Add suspend/resume support
  Documentation: dt-bindings: minimal documentation for MVEBU SDRAM controller

Signed-off-by: default avatarArnd Bergmann <arnd@arndb.de>
parents 756f80ce 6e6db2be

Documentation/devicetree/bindings/bus/mvebu-mbus.txt

+10 −7
Original line number Diff line number Diff line
@@ -48,9 +48,12 @@ Required properties: 
- compatible:	Should be set to "marvell,mbus-controller".



- reg:          Device's register space.

		Two entries are expected (see the examples below):

		the first one controls the devices decoding window and

		the second one controls the SDRAM decoding window.

		Two or three entries are expected (see the examples below):

		the first one controls the devices decoding window,

		the second one controls the SDRAM decoding window and

		the third controls the MBus bridge (only with the

		marvell,armada370-mbus and marvell,armadaxp-mbus

		compatible strings)



Example:
@@ -67,7 +70,7 @@ Example: 


			mbusc: mbus-controller@20000 {

				compatible = "marvell,mbus-controller";

				reg = <0x20000 0x100>, <0x20180 0x20>;

				reg = <0x20000 0x100>, <0x20180 0x20>, <0x20250 0x8>;

			};



			/* more children ...*/
@@ -126,7 +129,7 @@ are skipped. 


			mbusc: mbus-controller@20000 {

				compatible = "marvell,mbus-controller";

				reg = <0x20000 0x100>, <0x20180 0x20>;

				reg = <0x20000 0x100>, <0x20180 0x20>, <0x20250 0x8>;

			};



			/* more children ...*/
@@ -170,7 +173,7 @@ Using this macro, the above example would be: 


			mbusc: mbus-controller@20000 {

				compatible = "marvell,mbus-controller";

				reg = <0x20000 0x100>, <0x20180 0x20>;

				reg = <0x20000 0x100>, <0x20180 0x20>, <0x20250 0x8>;

			};



			/* other children */
@@ -266,7 +269,7 @@ See the example below, where a more complete device tree is shown: 
			ranges = <0 MBUS_ID(0xf0, 0x01) 0 0x100000>;



			mbusc: mbus-controller@20000 {

				reg = <0x20000 0x100>, <0x20180 0x20>;

				reg = <0x20000 0x100>, <0x20180 0x20>, <0x20250 0x8>;

			};



			interrupt-controller@20000 {

Documentation/devicetree/bindings/memory-controllers/mvebu-sdram-controller.txt

0 → 100644
+21 −0
Original line number Diff line number Diff line 
Device Tree bindings for MVEBU SDRAM controllers



The Marvell EBU SoCs all have a SDRAM controller. The SDRAM controller

differs from one SoC variant to another, but they also share a number

of commonalities.



For now, this Device Tree binding documentation only documents the

Armada XP SDRAM controller.



Required properties:



 - compatible: for Armada XP, "marvell,armada-xp-sdram-controller"

 - reg: a resource specifier for the register space, which should

   include all SDRAM controller registers as per the datasheet.



Example:



sdramc@1400 {

	compatible = "marvell,armada-xp-sdram-controller";

	reg = <0x1400 0x500>;

};

arch/arm/boot/dts/armada-370-xp.dtsi

+2 −1
Original line number Diff line number Diff line
@@ -180,7 +180,8 @@ 


			mbusc: mbus-controller@20000 {

				compatible = "marvell,mbus-controller";

				reg = <0x20000 0x100>, <0x20180 0x20>;

				reg = <0x20000 0x100>, <0x20180 0x20>,

				      <0x20250 0x8>;

			};



			mpic: interrupt-controller@20000 {

arch/arm/boot/dts/armada-xp-gp.dts

+18 −1
Original line number Diff line number Diff line
@@ -23,6 +23,7 @@ 
 */



/dts-v1/;

#include <dt-bindings/gpio/gpio.h>

#include "armada-xp-mv78460.dtsi"



/ {
@@ -48,6 +49,14 @@ 
		      <0x00000001 0x00000000 0x00000001 0x00000000>;

	};



	cpus {

		pm_pic {

			ctrl-gpios = <&gpio0 16 GPIO_ACTIVE_LOW>,

				     <&gpio0 17 GPIO_ACTIVE_LOW>,

				     <&gpio0 18 GPIO_ACTIVE_LOW>;

		};

	};



	soc {

		ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xf1000000 0x100000

			  MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000
@@ -115,7 +124,15 @@ 
			serial@12300 {

				status = "okay";

			};



			pinctrl {

				pinctrl-0 = <&pic_pins>;

				pinctrl-names = "default";

				pic_pins: pic-pins-0 {

					marvell,pins = "mpp16", "mpp17",

						       "mpp18";

					marvell,function = "gpio";

				};

			};

			sata@a0000 {

				nr-ports = <2>;

				status = "okay";

arch/arm/boot/dts/armada-xp.dtsi

+5 −0
Original line number Diff line number Diff line
@@ -35,6 +35,11 @@ 
		};



		internal-regs {

			sdramc@1400 {

				compatible = "marvell,armada-xp-sdram-controller";

				reg = <0x1400 0x500>;

			};



			L2: l2-cache {

				compatible = "marvell,aurora-system-cache";

				reg = <0x08000 0x1000>;

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