Unverified Commit ab4af605 authored Feb 20, 2018 by Andrea Parri Committed by Palmer Dabbelt Feb 26, 2018

riscv/barrier: Define __smp_{mb,rmb,wmb}

Introduce __smp_{mb,rmb,wmb}, and rely on the generic definitions
for smp_{mb,rmb,wmb}. A first consequence is that smp_{mb,rmb,wmb}
map to a compiler barrier on !SMP (while their definition remains
unchanged on SMP). As a further consequence, smp_load_acquire and
smp_store_release have "fence rw,rw" instead of "fence iorw,iorw".

Signed-off-by: Andrea Parri <parri.andrea@gmail.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>

parent 4a3928c6

arch/riscv/include/asm/barrier.h

+3 −3

Original line number	Diff line number	Diff line
		@@ -34,9 +34,9 @@
		#define wmb() RISCV_FENCE(ow,ow)

		/* These barriers do not need to enforce ordering on devices, just memory. */
		#define smp_mb() RISCV_FENCE(rw,rw)
		#define smp_rmb() RISCV_FENCE(r,r)
		#define smp_wmb() RISCV_FENCE(w,w)
		#define __smp_mb() RISCV_FENCE(rw,rw)
		#define __smp_rmb() RISCV_FENCE(r,r)
		#define __smp_wmb() RISCV_FENCE(w,w)

		/*
		* This is a very specific barrier: it's currently only used in two places in

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