Commit ab4510e9 authored by Madhavan Srinivasan's avatar Madhavan Srinivasan Committed by Michael Ellerman
Browse files

powerpc/perf: Add mem access events to sysfs 



Add mem-loads/mem-stores events to sysfs.
The event is formed based on raw event encoding.
Primary PMU event used here is PM_MRK_INST_CMPL
along with MMCRA[SM] modes and Thresholding bit

Signed-off-by: default avatarMadhavan Srinivasan <maddy@linux.vnet.ibm.com>
Signed-off-by: default avatarMichael Ellerman <mpe@ellerman.id.au>
parent 865a9432

arch/powerpc/perf/power9-events-list.h

+24 −0
Original line number Diff line number Diff line
@@ -97,3 +97,27 @@ EVENT(PM_MRK_DTLB_MISS_64K, 0x3d156) 
EVENT(PM_DTLB_MISS_16M,				0x4c056)

EVENT(PM_DTLB_MISS_1G,				0x4c05a)

EVENT(PM_MRK_DTLB_MISS_16M,			0x4c15e)



/*

 * Memory Access Events

 *

 * Primary PMU event used here is PM_MRK_INST_CMPL (0x401e0)

 * To enable capturing of memory profiling, these MMCRA bits

 * needs to be programmed and corresponding raw event format

 * encoding.

 *

 * MMCRA bits encoding needed are

 *     SM (Sampling Mode)

 *     EM (Eligibility for Random Sampling)

 *     TECE (Threshold Event Counter Event)

 *     TS (Threshold Start Event)

 *     TE (Threshold End Event)

 *

 * Corresponding Raw Encoding bits:

 *     sample [EM,SM]

 *     thresh_sel (TECE)

 *     thresh start (TS)

 *     thresh end (TE)

 */

EVENT(MEM_LOADS,				0x34340401e0)

EVENT(MEM_STORES,				0x343c0401e0)

arch/powerpc/perf/power9-pmu.c

+4 −0
Original line number Diff line number Diff line
@@ -160,6 +160,8 @@ GENERIC_EVENT_ATTR(branch-instructions, PM_BR_CMPL); 
GENERIC_EVENT_ATTR(branch-misses,		PM_BR_MPRED_CMPL);

GENERIC_EVENT_ATTR(cache-references,		PM_LD_REF_L1);

GENERIC_EVENT_ATTR(cache-misses,		PM_LD_MISS_L1_FIN);

GENERIC_EVENT_ATTR(mem-loads,			MEM_LOADS);

GENERIC_EVENT_ATTR(mem-stores,			MEM_STORES);



CACHE_EVENT_ATTR(L1-dcache-load-misses,		PM_LD_MISS_L1_FIN);

CACHE_EVENT_ATTR(L1-dcache-loads,		PM_LD_REF_L1);
@@ -185,6 +187,8 @@ static struct attribute *power9_events_attr[] = { 
	GENERIC_EVENT_PTR(PM_BR_MPRED_CMPL),

	GENERIC_EVENT_PTR(PM_LD_REF_L1),

	GENERIC_EVENT_PTR(PM_LD_MISS_L1_FIN),

	GENERIC_EVENT_PTR(MEM_LOADS),

	GENERIC_EVENT_PTR(MEM_STORES),

	CACHE_EVENT_PTR(PM_LD_MISS_L1_FIN),

	CACHE_EVENT_PTR(PM_LD_REF_L1),

	CACHE_EVENT_PTR(PM_L1_PREF),

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