Commit ab35c8a5 authored by Daniel Vetter's avatar Daniel Vetter
Browse files

Merge tag 'drm-intel-fixes-2019-08-02' of... 

Merge tag 'drm-intel-fixes-2019-08-02' of git://anongit.freedesktop.org/drm/drm-intel

 into drm-fixes

drm/i915 fixes for v5.3-rc3:
- GVT fixes
- Fix TBT aux powerwell
- Fix PSR2 training pattern duration
- Fix memory leak in runtime wakeref tracking
- Fix ICL memory bandwidth issue preventing planes from being enabled
- Fix OA mux configuration delays for accurate performance data
- Fix VLV/CHV DP audio cdclk frequency requirements
- Fix register whitelisting to fix a number of GL & Vulkan CTS tests
- Fix ICL perf register offsets
- Fix Gen11 Sampler Prefetch workaround, impacting dEQP tests
- Fix various gen2 tracepoints
- A number of GEM locking fixes addressing lockdep issues
- Fix idle engine reset, recover only active engines
- Fix incorrect MCR programming

Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
From: Jani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/87d0hnncgo.fsf@intel.com
parents f8981e03 4b9bb972

drivers/gpu/drm/i915/display/intel_bios.c

+1 −1
Original line number Diff line number Diff line
@@ -765,7 +765,7 @@ parse_psr(struct drm_i915_private *dev_priv, const struct bdb_header *bdb) 
	}



	if (bdb->version >= 226) {

		u32 wakeup_time = psr_table->psr2_tp2_tp3_wakeup_time;

		u32 wakeup_time = psr->psr2_tp2_tp3_wakeup_time;



		wakeup_time = (wakeup_time >> (2 * panel_type)) & 0x3;

		switch (wakeup_time) {

drivers/gpu/drm/i915/display/intel_bw.c

+10 −5
Original line number Diff line number Diff line
@@ -178,6 +178,8 @@ static int icl_get_bw_info(struct drm_i915_private *dev_priv) 
		clpchgroup = (sa->deburst * deinterleave / num_channels) << i;

		bi->num_planes = (ipqdepth - clpchgroup) / clpchgroup + 1;



		bi->num_qgv_points = qi.num_points;



		for (j = 0; j < qi.num_points; j++) {

			const struct intel_qgv_point *sp = &qi.points[j];

			int ct, bw;
@@ -195,7 +197,7 @@ static int icl_get_bw_info(struct drm_i915_private *dev_priv) 
			bi->deratedbw[j] = min(maxdebw,

					       bw * 9 / 10); /* 90% */



			DRM_DEBUG_KMS("BW%d / QGV %d: num_planes=%d deratedbw=%d\n",

			DRM_DEBUG_KMS("BW%d / QGV %d: num_planes=%d deratedbw=%u\n",

				      i, j, bi->num_planes, bi->deratedbw[j]);

		}
@@ -211,14 +213,17 @@ static unsigned int icl_max_bw(struct drm_i915_private *dev_priv, 
{

	int i;



	/* Did we initialize the bw limits successfully? */

	if (dev_priv->max_bw[0].num_planes == 0)

		return UINT_MAX;



	for (i = 0; i < ARRAY_SIZE(dev_priv->max_bw); i++) {

		const struct intel_bw_info *bi =

			&dev_priv->max_bw[i];



		/*

		 * Pcode will not expose all QGV points when

		 * SAGV is forced to off/min/med/max.

		 */

		if (qgv_point >= bi->num_qgv_points)

			return UINT_MAX;



		if (num_planes >= bi->num_planes)

			return bi->deratedbw[qgv_point];

	}

drivers/gpu/drm/i915/display/intel_cdclk.c

+11 −0
Original line number Diff line number Diff line
@@ -2239,6 +2239,17 @@ int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state) 
	if (crtc_state->has_audio && INTEL_GEN(dev_priv) >= 9)

		min_cdclk = max(2 * 96000, min_cdclk);



	/*

	 * "For DP audio configuration, cdclk frequency shall be set to

	 *  meet the following requirements:

	 *  DP Link Frequency(MHz) | Cdclk frequency(MHz)

	 *  270                    | 320 or higher

	 *  162                    | 200 or higher"

	 */

	if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&

	    intel_crtc_has_dp_encoder(crtc_state) && crtc_state->has_audio)

		min_cdclk = max(crtc_state->port_clock, min_cdclk);



	/*

	 * On Valleyview some DSI panels lose (v|h)sync when the clock is lower

	 * than 320000KHz.

drivers/gpu/drm/i915/display/intel_display.c

+2 −2
Original line number Diff line number Diff line
@@ -1839,7 +1839,7 @@ static void intel_enable_pipe(const struct intel_crtc_state *new_crtc_state) 
		/* FIXME: assert CPU port conditions for SNB+ */

	}



	trace_intel_pipe_enable(dev_priv, pipe);

	trace_intel_pipe_enable(crtc);



	reg = PIPECONF(cpu_transcoder);

	val = I915_READ(reg);
@@ -1880,7 +1880,7 @@ static void intel_disable_pipe(const struct intel_crtc_state *old_crtc_state) 
	 */

	assert_planes_disabled(crtc);



	trace_intel_pipe_disable(dev_priv, pipe);

	trace_intel_pipe_disable(crtc);



	reg = PIPECONF(cpu_transcoder);

	val = I915_READ(reg);

drivers/gpu/drm/i915/display/intel_display_power.c

+9 −2
Original line number Diff line number Diff line
@@ -438,16 +438,23 @@ icl_combo_phy_aux_power_well_disable(struct drm_i915_private *dev_priv, 
#define ICL_AUX_PW_TO_CH(pw_idx)	\

	((pw_idx) - ICL_PW_CTL_IDX_AUX_A + AUX_CH_A)



#define ICL_TBT_AUX_PW_TO_CH(pw_idx)	\

	((pw_idx) - ICL_PW_CTL_IDX_AUX_TBT1 + AUX_CH_C)



static void

icl_tc_phy_aux_power_well_enable(struct drm_i915_private *dev_priv,

				 struct i915_power_well *power_well)

{

	enum aux_ch aux_ch = ICL_AUX_PW_TO_CH(power_well->desc->hsw.idx);

	int pw_idx = power_well->desc->hsw.idx;

	bool is_tbt = power_well->desc->hsw.is_tc_tbt;

	enum aux_ch aux_ch;

	u32 val;



	aux_ch = is_tbt ? ICL_TBT_AUX_PW_TO_CH(pw_idx) :

			  ICL_AUX_PW_TO_CH(pw_idx);

	val = I915_READ(DP_AUX_CH_CTL(aux_ch));

	val &= ~DP_AUX_CH_CTL_TBT_IO;

	if (power_well->desc->hsw.is_tc_tbt)

	if (is_tbt)

		val |= DP_AUX_CH_CTL_TBT_IO;

	I915_WRITE(DP_AUX_CH_CTL(aux_ch), val);

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