Commit ab1f90f9 authored by Jani Nikula's avatar Jani Nikula Committed by Daniel Vetter
Browse files

drm/i915: rearrange vlv dp enable and pre_enable callbacks 



VLV wants encoder enabling before the pipe is up. This is currently
achieved through calling the ->enable callback early, right after the
->pre_enable callback, in valleyview_crtc_enable(). This loses both the
distinction between ->pre_enable and ->enable on VLV and the possibility
to use a hook at the end of the modeset sequence.

Rearrange the DP callbacks to make it possible to move ->enable call
later. Basically do everything in ->pre_enable on VLV, and make ->enable
a NOP.

There should be no functional changes.

v2: Rebase.

v3: Explain why this is needed in the commit message (Chris).

Signed-off-by: default avatarJani Nikula <jani.nikula@intel.com>
Reviewed-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent 0980a60f

drivers/gpu/drm/i915/intel_dp.c

+39 −34
Original line number Diff line number Diff line
@@ -1700,34 +1700,34 @@ static void intel_enable_dp(struct intel_encoder *encoder) 
	intel_dp_complete_link_train(intel_dp);

	intel_dp_stop_link_train(intel_dp);

	ironlake_edp_backlight_on(intel_dp);



	if (IS_VALLEYVIEW(dev)) {

		struct intel_digital_port *dport =

			enc_to_dig_port(&encoder->base);

		int channel = vlv_dport_to_channel(dport);



		vlv_wait_port_ready(dev_priv, channel);

}



static void vlv_enable_dp(struct intel_encoder *encoder)

{

}



static void intel_pre_enable_dp(struct intel_encoder *encoder)

{

	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);

	struct intel_digital_port *dport = dp_to_dig_port(intel_dp);

	struct drm_device *dev = encoder->base.dev;

	struct drm_i915_private *dev_priv = dev->dev_private;



	if (dport->port == PORT_A && !IS_VALLEYVIEW(dev))

	if (dport->port == PORT_A)

		ironlake_edp_pll_on(intel_dp);

}



	if (IS_VALLEYVIEW(dev)) {

		struct intel_crtc *intel_crtc =

			to_intel_crtc(encoder->base.crtc);

static void vlv_pre_enable_dp(struct intel_encoder *encoder)

{

	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);

	struct intel_digital_port *dport = dp_to_dig_port(intel_dp);

	struct drm_device *dev = encoder->base.dev;

	struct drm_i915_private *dev_priv = dev->dev_private;

	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);

	int port = vlv_dport_to_channel(dport);

	int pipe = intel_crtc->pipe;

	u32 val;



	mutex_lock(&dev_priv->dpio_lock);



	val = vlv_dpio_read(dev_priv, DPIO_DATA_LANE_A(port));

	val = 0;

	if (pipe)
@@ -1736,13 +1736,14 @@ static void intel_pre_enable_dp(struct intel_encoder *encoder) 
		val &= ~(1<<21);

	val |= 0x001000c4;

	vlv_dpio_write(dev_priv, DPIO_DATA_CHANNEL(port), val);

	vlv_dpio_write(dev_priv, DPIO_PCS_CLOCKBUF0(port), 0x00760018);

	vlv_dpio_write(dev_priv, DPIO_PCS_CLOCKBUF8(port), 0x00400888);



		vlv_dpio_write(dev_priv, DPIO_PCS_CLOCKBUF0(port),

				 0x00760018);

		vlv_dpio_write(dev_priv, DPIO_PCS_CLOCKBUF8(port),

				 0x00400888);

	mutex_unlock(&dev_priv->dpio_lock);

	}



	intel_enable_dp(encoder);



	vlv_wait_port_ready(dev_priv, port);

}



static void intel_dp_pre_pll_enable(struct intel_encoder *encoder)
@@ -3522,14 +3523,18 @@ intel_dp_init(struct drm_device *dev, int output_reg, enum port port) 


	intel_encoder->compute_config = intel_dp_compute_config;

	intel_encoder->mode_set = intel_dp_mode_set;

	intel_encoder->enable = intel_enable_dp;

	intel_encoder->pre_enable = intel_pre_enable_dp;

	intel_encoder->disable = intel_disable_dp;

	intel_encoder->post_disable = intel_post_disable_dp;

	intel_encoder->get_hw_state = intel_dp_get_hw_state;

	intel_encoder->get_config = intel_dp_get_config;

	if (IS_VALLEYVIEW(dev))

	if (IS_VALLEYVIEW(dev)) {

		intel_encoder->pre_pll_enable = intel_dp_pre_pll_enable;

		intel_encoder->pre_enable = vlv_pre_enable_dp;

		intel_encoder->enable = vlv_enable_dp;

	} else {

		intel_encoder->pre_enable = intel_pre_enable_dp;

		intel_encoder->enable = intel_enable_dp;

	}



	intel_dig_port->port = port;

	intel_dig_port->dp.output_reg = output_reg;

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