Merge branch 'v4.17-rc1'

Nuvoton NPCM Watchdog

Nuvoton NPCM timer module provides five 24-bit timer counters, and a watchdog.

The watchdog supports a pre-timeout interrupt that fires 10ms before the

expiry.

Required properties:

- compatible      : "nuvoton,npcm750-wdt" for NPCM750 (Poleg).

- reg             : Offset and length of the register set for the device.

- interrupts      : Contain the timer interrupt with flags for

                    falling edge.

Required clocking property, have to be one of:

- clocks          : phandle of timer reference clock.

- clock-frequency : The frequency in Hz of the clock that drives the NPCM7xx

                    timer (usually 25000000).

Optional properties:

- timeout-sec : Contains the watchdog timeout in seconds

Example:

timer@f000801c {

    compatible = "nuvoton,npcm750-wdt";

    interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;

    reg = <0xf000801c 0x4>;

    clocks = <&clk NPCM7XX_CLK_TIMER>;

};

	  This watchdog is used to reset the system and thus cannot be

	  compiled as a module.

config NPCM7XX_WATCHDOG

	bool "Nuvoton NPCM750 watchdog"

	depends on ARCH_NPCM || COMPILE_TEST

	default y if ARCH_NPCM750

	select WATCHDOG_CORE

	help

	  Say Y here to include Watchdog timer support for the

	  watchdog embedded into the NPCM7xx.

	  This watchdog is used to reset the system and thus cannot be

	  compiled as a module.

config TWL4030_WATCHDOG

	tristate "TWL4030 Watchdog"

	depends on TWL4030_CORE

obj-$(CONFIG_SUNXI_WATCHDOG) += sunxi_wdt.o

obj-$(CONFIG_RN5T618_WATCHDOG) += rn5t618_wdt.o

obj-$(CONFIG_COH901327_WATCHDOG) += coh901327_wdt.o

obj-$(CONFIG_NPCM7XX_WATCHDOG) += npcm_wdt.o

obj-$(CONFIG_STMP3XXX_RTC_WATCHDOG) += stmp3xxx_rtc_wdt.o

obj-$(CONFIG_NUC900_WATCHDOG) += nuc900_wdt.o

obj-$(CONFIG_TS4800_WATCHDOG) += ts4800_wdt.o

// SPDX-License-Identifier: GPL-2.0+

/*

 * drivers/watchdog/ar7_wdt.c

 *

 * National Semiconductor SCx200 Watchdog support

 * Copyright (c) 2001,2002 Christer Weinigel <wingel@nano-system.com>

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License as published by

 * the Free Software Foundation; either version 2 of the License, or

 * (at your option) any later version.

 *

 * This program is distributed in the hope that it will be useful,

 * but WITHOUT ANY WARRANTY; without even the implied warranty of

 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

 * GNU General Public License for more details.

 *

 * You should have received a copy of the GNU General Public License

 * along with this program; if not, write to the Free Software

 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA

 */

#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt

#define WDT_RELOAD_VALUE	0x04

#define WDT_RESTART		0x08

#define WDT_CTRL		0x0C

#define   WDT_CTRL_BOOT_SECONDARY	BIT(7)

#define   WDT_CTRL_RESET_MODE_SOC	(0x00 << 5)

#define   WDT_CTRL_RESET_MODE_FULL_CHIP	(0x01 << 5)

#define   WDT_CTRL_RESET_MODE_ARM_CPU	(0x10 << 5)

{

	struct aspeed_wdt *wdt = to_aspeed_wdt(wdd);

	wdt->ctrl &= ~WDT_CTRL_BOOT_SECONDARY;

	aspeed_wdt_enable(wdt, 128 * WDT_RATE_1MHZ / 1000);

	mdelay(1000);

	}

	if (of_property_read_bool(np, "aspeed,external-signal"))

		wdt->ctrl |= WDT_CTRL_WDT_EXT;

	if (of_property_read_bool(np, "aspeed,alt-boot"))

		wdt->ctrl |= WDT_CTRL_BOOT_SECONDARY;

	if (readl(wdt->base + WDT_CTRL) & WDT_CTRL_ENABLE)  {

		/*