Commit ab16b49c authored by Huazhong Tan's avatar Huazhong Tan Committed by Jakub Kicinski
Browse files

net: hns3: add support for querying maximum value of GL 



For maintainability and compatibility, add support for querying
the maximum value of GL.

Signed-off-by: default avatarHuazhong Tan <tanhuazhong@huawei.com>
Signed-off-by: default avatarJakub Kicinski <kuba@kernel.org>
parent 91bfae25

drivers/net/ethernet/hisilicon/hns3/hnae3.h

+1 −0
Original line number Diff line number Diff line
@@ -278,6 +278,7 @@ struct hnae3_dev_specs { 
	u16 rss_ind_tbl_size;

	u16 rss_key_size;

	u16 int_ql_max; /* max value of interrupt coalesce based on INT_QL */

	u16 max_int_gl; /* max value of interrupt coalesce based on INT_GL */

	u8 max_non_tso_bd_num; /* max BD number of one non-TSO packet */

};

drivers/net/ethernet/hisilicon/hns3/hns3_debugfs.c

+1 −0
Original line number Diff line number Diff line
@@ -349,6 +349,7 @@ static void hns3_dbg_dev_specs(struct hnae3_handle *h) 
	dev_info(priv->dev, "Desc num per RX queue: %u\n", kinfo->num_rx_desc);

	dev_info(priv->dev, "Total number of enabled TCs: %u\n", kinfo->num_tc);

	dev_info(priv->dev, "MAX INT QL: %u\n", dev_specs->int_ql_max);

	dev_info(priv->dev, "MAX INT GL: %u\n", dev_specs->max_int_gl);

}



static ssize_t hns3_dbg_cmd_read(struct file *filp, char __user *buffer,

drivers/net/ethernet/hisilicon/hns3/hns3_enet.h

+0 −1
Original line number Diff line number Diff line
@@ -420,7 +420,6 @@ enum hns3_flow_level_range { 
	HNS3_FLOW_ULTRA = 3,

};



#define HNS3_INT_GL_MAX			0x1FE0

#define HNS3_INT_GL_50K			0x0014

#define HNS3_INT_GL_20K			0x0032

#define HNS3_INT_GL_18K			0x0036

drivers/net/ethernet/hisilicon/hns3/hns3_ethtool.c

+8 −6
Original line number Diff line number Diff line
@@ -1130,19 +1130,21 @@ static int hns3_get_coalesce(struct net_device *netdev, 
static int hns3_check_gl_coalesce_para(struct net_device *netdev,

				       struct ethtool_coalesce *cmd)

{

	struct hnae3_handle *handle = hns3_get_handle(netdev);

	struct hnae3_ae_dev *ae_dev = pci_get_drvdata(handle->pdev);

	u32 rx_gl, tx_gl;



	if (cmd->rx_coalesce_usecs > HNS3_INT_GL_MAX) {

	if (cmd->rx_coalesce_usecs > ae_dev->dev_specs.max_int_gl) {

		netdev_err(netdev,

			   "Invalid rx-usecs value, rx-usecs range is 0-%d\n",

			   HNS3_INT_GL_MAX);

			   "invalid rx-usecs value, rx-usecs range is 0-%u\n",

			   ae_dev->dev_specs.max_int_gl);

		return -EINVAL;

	}



	if (cmd->tx_coalesce_usecs > HNS3_INT_GL_MAX) {

	if (cmd->tx_coalesce_usecs > ae_dev->dev_specs.max_int_gl) {

		netdev_err(netdev,

			   "Invalid tx-usecs value, tx-usecs range is 0-%d\n",

			   HNS3_INT_GL_MAX);

			   "invalid tx-usecs value, tx-usecs range is 0-%u\n",

			   ae_dev->dev_specs.max_int_gl);

		return -EINVAL;

	}

drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h

+8 −0
Original line number Diff line number Diff line
@@ -1103,6 +1103,14 @@ struct hclge_dev_specs_0_cmd { 
	__le32 max_tm_rate;

};



#define HCLGE_DEF_MAX_INT_GL		0x1FE0U



struct hclge_dev_specs_1_cmd {

	__le32 rsv0;

	__le16 max_int_gl;

	u8 rsv1[18];

};



int hclge_cmd_init(struct hclge_dev *hdev);

static inline void hclge_write_reg(void __iomem *base, u32 reg, u32 value)

{

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