Commit aab99b62 authored by David S. Miller's avatar David S. Miller
Browse files

Merge branch '100GbE' of git://git.kernel.org/pub/scm/linux/kernel/git/jkirsher/next-queue 



Tony Nguyen says:

====================
100GbE Intel Wired LAN Driver Updates 2020-07-23

This series contains updates to ice driver only.

Jake refactors ice_discover_caps() to reduce the number of AdminQ calls
made. Splits ice_parse_caps() to separate functions to update function
and device capabilities separately to allow for updating outside of
initialization.

Akeem adds power management support.

Paul G refactors FC and FEC code to aid in restoring of PHY settings
on media insertion. Implements lenient mode and link override support.
Adds link debug info and formats existing debug info to be more
readable. Adds support to check and report additional autoneg
capabilities. Implements the capability to detect media cage in order to
differentiate AUI types as Direct Attach or backplane.

Bruce implements Total Port Shutdown for devices that support it.

Lev renames low_power_ctrl field to lower_power_ctrl_an to be more
descriptive of the field.

Doug reports AOC types as media type fiber.

Paul S adds code to handle 1G SGMII PHY type.
====================

Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parents 2d6be17d c2b35226

drivers/net/ethernet/intel/ice/ice.h

+11 −0
Original line number Diff line number Diff line
@@ -222,6 +222,8 @@ enum ice_state { 
	__ICE_OICR_INTR_DIS,		/* Global OICR interrupt disabled */

	__ICE_MDD_VF_PRINT_PENDING,	/* set when MDD event handle */

	__ICE_VF_RESETS_DISABLED,	/* disable resets during ice_remove */

	__ICE_LINK_DEFAULT_OVERRIDE_PENDING,

	__ICE_PHY_INIT_COMPLETE,

	__ICE_STATE_NBITS		/* must be last */

};
@@ -357,12 +359,14 @@ enum ice_pf_flags { 
	ICE_FLAG_FD_ENA,

	ICE_FLAG_ADV_FEATURES,

	ICE_FLAG_LINK_DOWN_ON_CLOSE_ENA,

	ICE_FLAG_TOTAL_PORT_SHUTDOWN_ENA,

	ICE_FLAG_NO_MEDIA,

	ICE_FLAG_FW_LLDP_AGENT,

	ICE_FLAG_ETHTOOL_CTXT,		/* set when ethtool holds RTNL lock */

	ICE_FLAG_LEGACY_RX,

	ICE_FLAG_VF_TRUE_PROMISC_ENA,

	ICE_FLAG_MDD_AUTO_RESET_VF,

	ICE_FLAG_LINK_LENIENT_MODE_ENA,

	ICE_PF_FLAGS_NBITS		/* must be last */

};
@@ -423,6 +427,8 @@ struct ice_pf { 
	u16 empr_count;		/* EMP reset count */

	u16 pfr_count;		/* PF reset count */



	u8 wol_ena : 1;		/* software state of WoL */

	u32 wakeup_reason;	/* last wakeup reason */

	struct ice_hw_port_stats stats;

	struct ice_hw_port_stats stats_prev;

	struct ice_hw hw;
@@ -435,6 +441,10 @@ struct ice_pf { 
	u32 tx_timeout_recovery_level;

	char int_name[ICE_INT_NAME_STR_LEN];

	u32 sw_int_count;



	__le64 nvm_phy_type_lo; /* NVM PHY type low */

	__le64 nvm_phy_type_hi; /* NVM PHY type high */

	struct ice_link_default_override_tlv link_dflt_override;

};



struct ice_netdev_priv {
@@ -568,6 +578,7 @@ int ice_schedule_reset(struct ice_pf *pf, enum ice_reset_req reset); 
void ice_print_link_msg(struct ice_vsi *vsi, bool isup);

const char *ice_stat_str(enum ice_status stat_err);

const char *ice_aq_str(enum ice_aq_err aq_err);

bool ice_is_wol_supported(struct ice_pf *pf);

int

ice_fdir_write_fltr(struct ice_pf *pf, struct ice_fdir_fltr *input, bool add,

		    bool is_tun);

drivers/net/ethernet/intel/ice/ice_adminq_cmd.h

+63 −4
Original line number Diff line number Diff line
@@ -961,8 +961,11 @@ struct ice_aqc_get_phy_caps_data { 
#define ICE_AQC_GET_PHY_EN_MOD_QUAL			BIT(5)

#define ICE_AQC_PHY_EN_AUTO_FEC				BIT(7)

#define ICE_AQC_PHY_CAPS_MASK				ICE_M(0xff, 0)

	u8 low_power_ctrl;

	u8 low_power_ctrl_an;

#define ICE_AQC_PHY_EN_D3COLD_LOW_POWER_AUTONEG		BIT(0)

#define ICE_AQC_PHY_AN_EN_CLAUSE28			BIT(1)

#define ICE_AQC_PHY_AN_EN_CLAUSE73			BIT(2)

#define ICE_AQC_PHY_AN_EN_CLAUSE37			BIT(3)

	__le16 eee_cap;

#define ICE_AQC_PHY_EEE_EN_100BASE_TX			BIT(0)

#define ICE_AQC_PHY_EEE_EN_1000BASE_T			BIT(1)
@@ -983,12 +986,14 @@ struct ice_aqc_get_phy_caps_data { 
#define ICE_AQC_PHY_FEC_25G_RS_CLAUSE91_EN		BIT(6)

#define ICE_AQC_PHY_FEC_25G_KR_CLAUSE74_EN		BIT(7)

#define ICE_AQC_PHY_FEC_MASK				ICE_M(0xdf, 0)

	u8 rsvd1;	/* Byte 35 reserved */

	u8 module_compliance_enforcement;

#define ICE_AQC_MOD_ENFORCE_STRICT_MODE			BIT(0)

	u8 extended_compliance_code;

#define ICE_MODULE_TYPE_TOTAL_BYTE			3

	u8 module_type[ICE_MODULE_TYPE_TOTAL_BYTE];

#define ICE_AQC_MOD_TYPE_BYTE0_SFP_PLUS			0xA0

#define ICE_AQC_MOD_TYPE_BYTE0_QSFP_PLUS		0x80

#define ICE_AQC_MOD_TYPE_IDENT				1

#define ICE_AQC_MOD_TYPE_BYTE1_SFP_PLUS_CU_PASSIVE	BIT(0)

#define ICE_AQC_MOD_TYPE_BYTE1_SFP_PLUS_CU_ACTIVE	BIT(1)

#define ICE_AQC_MOD_TYPE_BYTE1_10G_BASE_SR		BIT(4)
@@ -1032,11 +1037,11 @@ struct ice_aqc_set_phy_cfg_data { 
#define ICE_AQ_PHY_ENA_AUTO_LINK_UPDT	BIT(5)

#define ICE_AQ_PHY_ENA_LESM		BIT(6)

#define ICE_AQ_PHY_ENA_AUTO_FEC		BIT(7)

	u8 low_power_ctrl;

	u8 low_power_ctrl_an;

	__le16 eee_cap; /* Value from ice_aqc_get_phy_caps */

	__le16 eeer_value;

	u8 link_fec_opt; /* Use defines from ice_aqc_get_phy_caps */

	u8 rsvd1;

	u8 module_compliance_enforcement;

};



/* Set MAC Config command data structure (direct 0x0603) */
@@ -1147,6 +1152,7 @@ struct ice_aqc_get_link_status_data { 
#define ICE_AQ_LINK_PWR_QSFP_CLASS_3	2

#define ICE_AQ_LINK_PWR_QSFP_CLASS_4	3

	__le16 link_speed;

#define ICE_AQ_LINK_SPEED_M		0x7FF

#define ICE_AQ_LINK_SPEED_10MB		BIT(0)

#define ICE_AQ_LINK_SPEED_100MB		BIT(1)

#define ICE_AQ_LINK_SPEED_1000MB	BIT(2)
@@ -1189,6 +1195,57 @@ struct ice_aqc_set_mac_lb { 
	u8 reserved[15];

};



struct ice_aqc_link_topo_addr {

	u8 lport_num;

	u8 lport_num_valid;

#define ICE_AQC_LINK_TOPO_PORT_NUM_VALID	BIT(0)

	u8 node_type_ctx;

#define ICE_AQC_LINK_TOPO_NODE_TYPE_S		0

#define ICE_AQC_LINK_TOPO_NODE_TYPE_M	(0xF << ICE_AQC_LINK_TOPO_NODE_TYPE_S)

#define ICE_AQC_LINK_TOPO_NODE_TYPE_PHY		0

#define ICE_AQC_LINK_TOPO_NODE_TYPE_GPIO_CTRL	1

#define ICE_AQC_LINK_TOPO_NODE_TYPE_MUX_CTRL	2

#define ICE_AQC_LINK_TOPO_NODE_TYPE_LED_CTRL	3

#define ICE_AQC_LINK_TOPO_NODE_TYPE_LED		4

#define ICE_AQC_LINK_TOPO_NODE_TYPE_THERMAL	5

#define ICE_AQC_LINK_TOPO_NODE_TYPE_CAGE	6

#define ICE_AQC_LINK_TOPO_NODE_TYPE_MEZZ	7

#define ICE_AQC_LINK_TOPO_NODE_TYPE_ID_EEPROM	8

#define ICE_AQC_LINK_TOPO_NODE_CTX_S		4

#define ICE_AQC_LINK_TOPO_NODE_CTX_M		\

				(0xF << ICE_AQC_LINK_TOPO_NODE_CTX_S)

#define ICE_AQC_LINK_TOPO_NODE_CTX_GLOBAL	0

#define ICE_AQC_LINK_TOPO_NODE_CTX_BOARD	1

#define ICE_AQC_LINK_TOPO_NODE_CTX_PORT		2

#define ICE_AQC_LINK_TOPO_NODE_CTX_NODE		3

#define ICE_AQC_LINK_TOPO_NODE_CTX_PROVIDED	4

#define ICE_AQC_LINK_TOPO_NODE_CTX_OVERRIDE	5

	u8 index;

	__le16 handle;

#define ICE_AQC_LINK_TOPO_HANDLE_S	0

#define ICE_AQC_LINK_TOPO_HANDLE_M	(0x3FF << ICE_AQC_LINK_TOPO_HANDLE_S)

/* Used to decode the handle field */

#define ICE_AQC_LINK_TOPO_HANDLE_BRD_TYPE_M	BIT(9)

#define ICE_AQC_LINK_TOPO_HANDLE_BRD_TYPE_LOM	BIT(9)

#define ICE_AQC_LINK_TOPO_HANDLE_BRD_TYPE_MEZZ	0

#define ICE_AQC_LINK_TOPO_HANDLE_NODE_S		0

/* In case of a Mezzanine type */

#define ICE_AQC_LINK_TOPO_HANDLE_MEZZ_NODE_M	\

				(0x3F << ICE_AQC_LINK_TOPO_HANDLE_NODE_S)

#define ICE_AQC_LINK_TOPO_HANDLE_MEZZ_S	6

#define ICE_AQC_LINK_TOPO_HANDLE_MEZZ_M	(0x7 << ICE_AQC_LINK_TOPO_HANDLE_MEZZ_S)

/* In case of a LOM type */

#define ICE_AQC_LINK_TOPO_HANDLE_LOM_NODE_M	\

				(0x1FF << ICE_AQC_LINK_TOPO_HANDLE_NODE_S)

};



/* Get Link Topology Handle (direct, 0x06E0) */

struct ice_aqc_get_link_topo {

	struct ice_aqc_link_topo_addr addr;

	u8 node_part_num;

	u8 rsvd[9];

};



/* Set Port Identification LED (direct, 0x06E9) */

struct ice_aqc_set_port_id_led {

	u8 lport_num;
@@ -1759,6 +1816,7 @@ struct ice_aq_desc { 
		struct ice_aqc_set_event_mask set_event_mask;

		struct ice_aqc_get_link_status get_link_status;

		struct ice_aqc_event_lan_overflow lan_overflow;

		struct ice_aqc_get_link_topo get_link_topo;

	} params;

};
@@ -1858,6 +1916,7 @@ enum ice_adminq_opc { 
	ice_aqc_opc_get_link_status			= 0x0607,

	ice_aqc_opc_set_event_mask			= 0x0613,

	ice_aqc_opc_set_mac_lb				= 0x0620,

	ice_aqc_opc_get_link_topo			= 0x06E0,

	ice_aqc_opc_set_port_id_led			= 0x06E9,

	ice_aqc_opc_sff_eeprom				= 0x06EE,

drivers/net/ethernet/intel/ice/ice_common.c

+932 −297

File changed.

Preview size limit exceeded, changes collapsed.

drivers/net/ethernet/intel/ice/ice_common.h

+20 −4
Original line number Diff line number Diff line
@@ -98,17 +98,33 @@ ice_aq_manage_mac_write(struct ice_hw *hw, const u8 *mac_addr, u8 flags, 
			struct ice_sq_cd *cd);

enum ice_status ice_clear_pf_cfg(struct ice_hw *hw);

enum ice_status

ice_aq_set_phy_cfg(struct ice_hw *hw, u8 lport,

ice_aq_set_phy_cfg(struct ice_hw *hw, struct ice_port_info *pi,

		   struct ice_aqc_set_phy_cfg_data *cfg, struct ice_sq_cd *cd);

bool ice_fw_supports_link_override(struct ice_hw *hw);

enum ice_status

ice_get_link_default_override(struct ice_link_default_override_tlv *ldo,

			      struct ice_port_info *pi);

bool ice_is_phy_caps_an_enabled(struct ice_aqc_get_phy_caps_data *caps);



enum ice_fc_mode ice_caps_to_fc_mode(u8 caps);

enum ice_fec_mode ice_caps_to_fec_mode(u8 caps, u8 fec_options);

enum ice_status

ice_set_fc(struct ice_port_info *pi, u8 *aq_failures,

	   bool ena_auto_link_update);

enum ice_status

ice_cfg_phy_fc(struct ice_port_info *pi, struct ice_aqc_set_phy_cfg_data *cfg,

	       enum ice_fc_mode fc);

bool

ice_phy_caps_equals_cfg(struct ice_aqc_get_phy_caps_data *caps,

			struct ice_aqc_set_phy_cfg_data *cfg);

void

ice_cfg_phy_fec(struct ice_aqc_set_phy_cfg_data *cfg, enum ice_fec_mode fec);

void

ice_copy_phy_caps_to_cfg(struct ice_aqc_get_phy_caps_data *caps,

ice_copy_phy_caps_to_cfg(struct ice_port_info *pi,

			 struct ice_aqc_get_phy_caps_data *caps,

			 struct ice_aqc_set_phy_cfg_data *cfg);

enum ice_status

ice_cfg_phy_fec(struct ice_port_info *pi, struct ice_aqc_set_phy_cfg_data *cfg,

		enum ice_fec_mode fec);

enum ice_status

ice_aq_set_link_restart_an(struct ice_port_info *pi, bool ena_link,

			   struct ice_sq_cd *cd);

enum ice_status

drivers/net/ethernet/intel/ice/ice_ethtool.c

+455 −285

File changed.

Preview size limit exceeded, changes collapsed.

CRA Git | Maintained and supported by SUSTech CRA and CCSE