Commit aab6bf50 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'arm64-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux 

Pull arm64 fixes from Will Deacon:
 "The diffstat is a bit spread out thanks to an invasive CPU erratum
  workaround which missed the merge window and also a bunch of fixes to
  the recently added MTE selftests.

   - Fixes to MTE kselftests

   - Fix return code from KVM Spectre-v2 hypercall

   - Build fixes for ld.lld and Clang's infamous integrated assembler

   - Ensure RCU is up and running before we use printk()

   - Workaround for Cortex-A77 erratum 1508412

   - Fix linker warnings from unexpected ELF sections

   - Ensure PE/COFF sections are 64k aligned"

* tag 'arm64-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux:
  arm64: Change .weak to SYM_FUNC_START_WEAK_PI for arch/arm64/lib/mem*.S
  arm64/smp: Move rcu_cpu_starting() earlier
  arm64: Add workaround for Arm Cortex-A77 erratum 1508412
  arm64: Add part number for Arm Cortex-A77
  arm64: mte: Document that user PSTATE.TCO is ignored by kernel uaccess
  module: use hidden visibility for weak symbol references
  arm64: efi: increase EFI PE/COFF header padding to 64 KB
  arm64: vmlinux.lds: account for spurious empty .igot.plt sections
  kselftest/arm64: Fix check_user_mem test
  kselftest/arm64: Fix check_ksm_options test
  kselftest/arm64: Fix check_mmap_options test
  kselftest/arm64: Fix check_child_memory test
  kselftest/arm64: Fix check_tags_inclusion test
  kselftest/arm64: Fix check_buffer_fill test
  arm64: avoid -Woverride-init warning
  KVM: arm64: ARM_SMCCC_ARCH_WORKAROUND_1 doesn't return SMCCC_RET_NOT_REQUIRED
  arm64: vdso32: Allow ld.lld to properly link the VDSO
parents 11ad2a73 ec9d7807

Documentation/arm64/memory-tagging-extension.rst

+3 −1
Original line number Diff line number Diff line
@@ -102,7 +102,9 @@ applications. 
system call) are not checked if the user thread tag checking mode is

``PR_MTE_TCF_NONE`` or ``PR_MTE_TCF_ASYNC``. If the tag checking mode is

``PR_MTE_TCF_SYNC``, the kernel makes a best effort to check its user

address accesses, however it cannot always guarantee it.

address accesses, however it cannot always guarantee it. Kernel accesses

to user addresses are always performed with an effective ``PSTATE.TCO``

value of zero, regardless of the user configuration.



Excluding Tags in the ``IRG``, ``ADDG`` and ``SUBG`` instructions

-----------------------------------------------------------------

Documentation/arm64/silicon-errata.rst

+2 −0
Original line number Diff line number Diff line
@@ -90,6 +90,8 @@ stable kernels. 
+----------------+-----------------+-----------------+-----------------------------+

| ARM            | Cortex-A76      | #1463225        | ARM64_ERRATUM_1463225       |

+----------------+-----------------+-----------------+-----------------------------+

| ARM            | Cortex-A77      | #1508412        | ARM64_ERRATUM_1508412       |

+----------------+-----------------+-----------------+-----------------------------+

| ARM            | Neoverse-N1     | #1188873,1418040| ARM64_ERRATUM_1418040       |

+----------------+-----------------+-----------------+-----------------------------+

| ARM            | Neoverse-N1     | #1349291        | N/A                         |

arch/arm64/Kconfig

+20 −0
Original line number Diff line number Diff line
@@ -636,6 +636,26 @@ config ARM64_ERRATUM_1542419 


	  If unsure, say Y.



config ARM64_ERRATUM_1508412

	bool "Cortex-A77: 1508412: workaround deadlock on sequence of NC/Device load and store exclusive or PAR read"

	default y

	help

	  This option adds a workaround for Arm Cortex-A77 erratum 1508412.



	  Affected Cortex-A77 cores (r0p0, r1p0) could deadlock on a sequence

	  of a store-exclusive or read of PAR_EL1 and a load with device or

	  non-cacheable memory attributes. The workaround depends on a firmware

	  counterpart.



	  KVM guests must also have the workaround implemented or they can

	  deadlock the system.



	  Work around the issue by inserting DMB SY barriers around PAR_EL1

	  register reads and warning KVM users. The DMB barrier is sufficient

	  to prevent a speculative PAR_EL1 read.



	  If unsure, say Y.



config CAVIUM_ERRATUM_22375

	bool "Cavium erratum 22375, 24313"

	default y

arch/arm64/include/asm/cache.h

+1 −0
Original line number Diff line number Diff line
@@ -24,6 +24,7 @@ 
#define CTR_L1IP(ctr)		(((ctr) >> CTR_L1IP_SHIFT) & CTR_L1IP_MASK)



#define ICACHE_POLICY_VPIPT	0

#define ICACHE_POLICY_RESERVED	1

#define ICACHE_POLICY_VIPT	2

#define ICACHE_POLICY_PIPT	3

arch/arm64/include/asm/cpucaps.h

+2 −1
Original line number Diff line number Diff line
@@ -65,7 +65,8 @@ 
#define ARM64_HAS_ARMv8_4_TTL			55

#define ARM64_HAS_TLB_RANGE			56

#define ARM64_MTE				57

#define ARM64_WORKAROUND_1508412		58



#define ARM64_NCAPS				58

#define ARM64_NCAPS				59



#endif /* __ASM_CPUCAPS_H */

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