iommu/arm-smmu: add NVIDIA implementation for ARM MMU-500 usage (aab5a1c8) · Commits · 戴 / test

MAINTAINERS

+2 −0

Original line number	Diff line number	Diff line
		@@ -16810,8 +16810,10 @@ F: drivers/i2c/busses/i2c-tegra.c

		TEGRA IOMMU DRIVERS
		M: Thierry Reding <thierry.reding@gmail.com>
		R: Krishna Reddy <vdumpa@nvidia.com>
		L: linux-tegra@vger.kernel.org
		S: Supported
		F: drivers/iommu/arm-smmu-nvidia.c
		F: drivers/iommu/tegra*

		TEGRA KBC DRIVER

drivers/iommu/Makefile

+1 −1

Original line number	Diff line number	Diff line
		@@ -15,7 +15,7 @@ obj-$(CONFIG_AMD_IOMMU) += amd/iommu.o amd/init.o amd/quirks.o
		obj-$(CONFIG_AMD_IOMMU_DEBUGFS) += amd/debugfs.o
		obj-$(CONFIG_AMD_IOMMU_V2) += amd/iommu_v2.o
		obj-$(CONFIG_ARM_SMMU) += arm_smmu.o
		arm_smmu-objs += arm-smmu.o arm-smmu-impl.o arm-smmu-qcom.o
		arm_smmu-objs += arm-smmu.o arm-smmu-impl.o arm-smmu-nvidia.o arm-smmu-qcom.o
		obj-$(CONFIG_ARM_SMMU_V3) += arm-smmu-v3.o
		obj-$(CONFIG_DMAR_TABLE) += intel/dmar.o
		obj-$(CONFIG_INTEL_IOMMU) += intel/iommu.o intel/pasid.o

drivers/iommu/arm-smmu-impl.c

+3 −0

Original line number	Diff line number	Diff line
		@@ -213,6 +213,9 @@ struct arm_smmu_device arm_smmu_impl_init(struct arm_smmu_device smmu)
		if (of_property_read_bool(np, "calxeda,smmu-secure-config-access"))
		smmu->impl = &calxeda_impl;

		if (of_device_is_compatible(np, "nvidia,tegra194-smmu"))
		return nvidia_smmu_impl_init(smmu);

		if (of_device_is_compatible(np, "qcom,sdm845-smmu-500") \|\|
		of_device_is_compatible(np, "qcom,sc7180-smmu-500") \|\|
		of_device_is_compatible(np, "qcom,sm8150-smmu-500") \|\|

drivers/iommu/arm-smmu-nvidia.c

0 → 100644

+179 −0

Original line number	Diff line number	Diff line
		// SPDX-License-Identifier: GPL-2.0-only
		// Copyright (C) 2019-2020 NVIDIA CORPORATION. All rights reserved.

		#include <linux/bitfield.h>
		#include <linux/delay.h>
		#include <linux/of.h>
		#include <linux/platform_device.h>
		#include <linux/slab.h>

		#include "arm-smmu.h"

		/*
		* Tegra194 has three ARM MMU-500 Instances.
		* Two of them are used together and must be programmed identically for
		* interleaved IOVA accesses across them and translates accesses from
		* non-isochronous HW devices.
		* Third one is used for translating accesses from isochronous HW devices.
		* This implementation supports programming of the two instances that must
		* be programmed identically.
		* The third instance usage is through standard arm-smmu driver itself and
		* is out of scope of this implementation.
		*/
		#define NUM_SMMU_INSTANCES 2

		struct nvidia_smmu {
		struct arm_smmu_device smmu;
		void __iomem *bases[NUM_SMMU_INSTANCES];
		};

		static inline void __iomem nvidia_smmu_page(struct arm_smmu_device smmu,
		unsigned int inst, int page)
		{
		struct nvidia_smmu *nvidia_smmu;

		nvidia_smmu = container_of(smmu, struct nvidia_smmu, smmu);
		return nvidia_smmu->bases[inst] + (page << smmu->pgshift);
		}

		static u32 nvidia_smmu_read_reg(struct arm_smmu_device *smmu,
		int page, int offset)
		{
		void __iomem *reg = nvidia_smmu_page(smmu, 0, page) + offset;

		return readl_relaxed(reg);
		}

		static void nvidia_smmu_write_reg(struct arm_smmu_device *smmu,
		int page, int offset, u32 val)
		{
		unsigned int i;

		for (i = 0; i < NUM_SMMU_INSTANCES; i++) {
		void __iomem *reg = nvidia_smmu_page(smmu, i, page) + offset;

		writel_relaxed(val, reg);
		}
		}

		static u64 nvidia_smmu_read_reg64(struct arm_smmu_device *smmu,
		int page, int offset)
		{
		void __iomem *reg = nvidia_smmu_page(smmu, 0, page) + offset;

		return readq_relaxed(reg);
		}

		static void nvidia_smmu_write_reg64(struct arm_smmu_device *smmu,
		int page, int offset, u64 val)
		{
		unsigned int i;

		for (i = 0; i < NUM_SMMU_INSTANCES; i++) {
		void __iomem *reg = nvidia_smmu_page(smmu, i, page) + offset;

		writeq_relaxed(val, reg);
		}
		}

		static void nvidia_smmu_tlb_sync(struct arm_smmu_device *smmu, int page,
		int sync, int status)
		{
		unsigned int delay;

		arm_smmu_writel(smmu, page, sync, 0);

		for (delay = 1; delay < TLB_LOOP_TIMEOUT; delay *= 2) {
		unsigned int spin_cnt;

		for (spin_cnt = TLB_SPIN_COUNT; spin_cnt > 0; spin_cnt--) {
		u32 val = 0;
		unsigned int i;

		for (i = 0; i < NUM_SMMU_INSTANCES; i++) {
		void __iomem *reg;

		reg = nvidia_smmu_page(smmu, i, page) + status;
		val \|= readl_relaxed(reg);
		}

		if (!(val & ARM_SMMU_sTLBGSTATUS_GSACTIVE))
		return;

		cpu_relax();
		}

		udelay(delay);
		}

		dev_err_ratelimited(smmu->dev,
		"TLB sync timed out -- SMMU may be deadlocked\n");
		}

		static int nvidia_smmu_reset(struct arm_smmu_device *smmu)
		{
		unsigned int i;

		for (i = 0; i < NUM_SMMU_INSTANCES; i++) {
		u32 val;
		void __iomem *reg = nvidia_smmu_page(smmu, i, ARM_SMMU_GR0) +
		ARM_SMMU_GR0_sGFSR;

		/* clear global FSR */
		val = readl_relaxed(reg);
		writel_relaxed(val, reg);
		}

		return 0;
		}

		static const struct arm_smmu_impl nvidia_smmu_impl = {
		.read_reg = nvidia_smmu_read_reg,
		.write_reg = nvidia_smmu_write_reg,
		.read_reg64 = nvidia_smmu_read_reg64,
		.write_reg64 = nvidia_smmu_write_reg64,
		.reset = nvidia_smmu_reset,
		.tlb_sync = nvidia_smmu_tlb_sync,
		};

		struct arm_smmu_device nvidia_smmu_impl_init(struct arm_smmu_device smmu)
		{
		struct resource *res;
		struct device *dev = smmu->dev;
		struct nvidia_smmu *nvidia_smmu;
		struct platform_device *pdev = to_platform_device(dev);

		nvidia_smmu = devm_kzalloc(dev, sizeof(*nvidia_smmu), GFP_KERNEL);
		if (!nvidia_smmu)
		return ERR_PTR(-ENOMEM);

		/*
		* Copy the data from struct arm_smmu_device *smmu allocated in
		* arm-smmu.c. The smmu from struct nvidia_smmu replaces the smmu
		* pointer used in arm-smmu.c once this function returns.
		* This is necessary to derive nvidia_smmu from smmu pointer passed
		* through arm_smmu_impl function calls subsequently.
		*/
		nvidia_smmu->smmu = *smmu;
		/* Instance 0 is ioremapped by arm-smmu.c. */
		nvidia_smmu->bases[0] = smmu->base;

		res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
		if (!res)
		return ERR_PTR(-ENODEV);

		nvidia_smmu->bases[1] = devm_ioremap_resource(dev, res);
		if (IS_ERR(nvidia_smmu->bases[1]))
		return ERR_CAST(nvidia_smmu->bases[1]);

		nvidia_smmu->smmu.impl = &nvidia_smmu_impl;

		/*
		* Free the struct arm_smmu_device *smmu allocated in arm-smmu.c.
		* Once this function returns, arm-smmu.c would use arm_smmu_device
		* allocated as part of struct nvidia_smmu.
		*/
		devm_kfree(dev, smmu);

		return &nvidia_smmu->smmu;
		}

drivers/iommu/arm-smmu.c

+1 −0

Original line number	Diff line number	Diff line
		@@ -1946,6 +1946,7 @@ static const struct of_device_id arm_smmu_of_match[] = {
		{ .compatible = "arm,mmu-401", .data = &arm_mmu401 },
		{ .compatible = "arm,mmu-500", .data = &arm_mmu500 },
		{ .compatible = "cavium,smmu-v2", .data = &cavium_smmuv2 },
		{ .compatible = "nvidia,smmu-500", .data = &arm_mmu500 },
		{ .compatible = "qcom,smmu-v2", .data = &qcom_smmuv2 },
		{ },
		};

Admin message